FreeCalypso > hg > fc-selenite

annotate src/cs/system/main/gcc/exceptions.S @ 134:7d50d8d13711

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FFS code sync with Magnetite + gcc version fix This change brings the new flash autodetection for FC and Pirelli targets from Magnetite, and should also fix the gcc version for C1xx and gtamodem targets, which were previously broken because they used TI's original flash autodetect code (which operates at address 0) while the boot ROM is mapped there.
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 11 Dec 2018 08:43:25 +0000
parents 92fde62400ef
children
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1 /*
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2 * This module contains ARM exception handlers which used to be
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3 * in chipsetsw/system/Main/int.s in TI's original version.
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4 */
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5
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6 .text
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7 .code 32
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8
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9 @ layout of xdump buffer:
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10 @ struct xdump_s {
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11 @ long registers[16] // svc mode registers
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12 @ long cpsr // svc mode CPSR
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13 @ long exception // magic word + index of vector taken
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14 @ long stack[20] // bottom 20 words of usr mode stack
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15 @ }
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16
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17 .globl _arm_undefined
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18 _arm_undefined:
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19 @ store r12 for Xdump_buffer pointer, r11 for index
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20 stmfd r13!,{r11,r12}
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21 mov r11,#1
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22 b save_regs
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24 .globl _arm_swi
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25 _arm_swi:
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26 @ store r12 for Xdump_buffer pointer, r11 for index
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27 stmfd r13!,{r11,r12}
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28 mov r11,#2
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29 b save_regs
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31 .globl _arm_abort_prefetch
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32 _arm_abort_prefetch:
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33 @ store r12 for Xdump_buffer pointer, r11 for index
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34 stmfd r13!,{r11,r12}
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35 mov r11,#3
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36 b save_regs
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38 .globl _arm_abort_data
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39 _arm_abort_data:
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40 @ store r12 for Xdump_buffer pointer, r11 for index
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41 stmfd r13!,{r11,r12}
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42 mov r11,#4
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43 b save_regs
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45 .globl _arm_reserved
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46 _arm_reserved:
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47 ldr r13,=_Except_Stack_SP @ mode unknown
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48 @ store r12 for Xdump_buffer pointer, r11 for index
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49 stmfd r13!,{r11,r12}
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50 mov r11,#5
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51 b save_regs
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52
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53 save_regs:
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54 ldr r12,=xdump_buffer
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55 str r14,[r12,#4*15] @ save r14_abt (original PC) into r15 slot
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57 stmia r12,{r0-r10} @ save unbanked registers (except r11 and r12)
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58 ldmfd r13!,{r0,r1} @ get original r11 and r12
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59 str r0,[r12,#4*11] @ save original r11
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60 str r1,[r12,#4*12] @ save original r12
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61 mrs r0,spsr @ get original psr
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62 str r0,[r12,#4*16] @ save original cpsr
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64 mrs r1,cpsr @ save mode psr
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65 bic r2,r1,#0x1f @ psr with mode bits cleared
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66 and r0,r0,#0x1f @ get original mode bits
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67 add r0,r0,r2
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69 msr cpsr,r0 @ move to pre-exception mode
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70 str r13,[r12,#4*13] @ save original SP
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71 str r14,[r12,#4*14] @ save original LR
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72 msr cpsr,r1 @ restore mode psr
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73
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74 @ r11 has original index
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75 orr r10,r11,#0xDE<<24 @ r10 = 0xDEAD0000 + index of vector taken
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76 orr r10,r10,#0xAD<<16
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77 str r10,[r12,#4*17] @ save magic + index
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78
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79 mov r0,r11 @ put index into 1st argument
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80 b dar_exception
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82 @ the second part
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83
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84 /*
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85 * For the SP-in-RAM validity check, we use the following simplification:
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86 * it doesn't really matter what the actual IRAM and XRAM sizes are on
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87 * any given target, as the address decoder hooked up to the ARM7TDMI core
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88 * always decodes the full 8 MiB address range for each, causing the
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89 * actual memories to be aliased multiple times in those two ranges.
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90 * Furthermore, the XRAM address range falls right after the IRAM one,
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91 * thus we can get away with only a single range check.
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92 */
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93
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94 #define RAM_LOW 0x00800000
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95 #define RAM_HIGH 0x01800000
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96
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97 #define XDUMP_STACK_SIZE 20
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98
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99 .globl exception
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100 exception:
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101 ldr r12,=xdump_buffer
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102 ldr r11,[r12,#4*13] @ get svc mode r13
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103 add r12,r12,#4*18 @ base of stack buffer
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104
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105 @ check if svc r13(sp) is within internal/external RAM.
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106 @ It *could* be invalid.
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107 cmp r11,#RAM_LOW
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108 blt nostack
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109 mov r0,#RAM_HIGH
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110 sub r0,r0,#XDUMP_STACK_SIZE
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111 cmp r11,r0
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112 bge nostack
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113
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114 stack_range:
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115 ldmfd r11!,{r0-r9} @ copy ten stack words..
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116 stmia r12!,{r0-r9}
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117 ldmfd r11!,{r0-r9} @ copy ten stack words..
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
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118 stmia r12!,{r0-r9}
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
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119
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
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120 nostack:
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
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121 @ we're finished saving all state.
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
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122 @ Now execute C code for more flexibility.
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
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123 @ set up a stack for this C call
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
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124 ldr sp,=_Stack_segment_end
92fde62400ef .../gcc/exceptions.S: added 2nd part that was missing in Citrine
Mychaela Falconia <falcon@freecalypso.org>
parents: 78
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125 b dar_reset