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comparison fpga/mcsi-rx/sync_inputs.v @ 1:b3190839cce3

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first FPGA version, MCSI Rx only
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 11 Oct 2024 21:11:24 +0000
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0:4624f3da093a 1:b3190839cce3
1 /*
2 * This Verilog module captures the input synchronizer logic: passing
3 * all 3 MCSI inputs through double-DFF synchronizers to bring them into
4 * our internal clock domain.
5 */
6
7 module sync_inputs (IntClk, MCSI_CLK_raw, MCSI_CLK_sync, MCSI_FS_raw,
8 MCSI_FS_sync, MCSI_Din_raw, MCSI_Din_sync);
9
10 input IntClk;
11 input MCSI_CLK_raw, MCSI_FS_raw, MCSI_Din_raw;
12 output MCSI_CLK_sync, MCSI_FS_sync, MCSI_Din_sync;
13 reg MCSI_CLK_sync, MCSI_FS_sync, MCSI_Din_sync;
14
15 reg MCSI_CLK_sync1, MCSI_FS_sync1, MCSI_Din_sync1;
16
17 always @(posedge IntClk)
18 MCSI_CLK_sync1 <= MCSI_CLK_raw;
19
20 always @(posedge IntClk)
21 MCSI_CLK_sync <= MCSI_CLK_sync1;
22
23 always @(posedge IntClk)
24 MCSI_FS_sync1 <= MCSI_FS_raw;
25
26 always @(posedge IntClk)
27 MCSI_FS_sync <= MCSI_FS_sync1;
28
29 always @(posedge IntClk)
30 MCSI_Din_sync1 <= MCSI_Din_raw;
31
32 always @(posedge IntClk)
33 MCSI_Din_sync <= MCSI_Din_sync1;
34
35 endmodule