FreeCalypso > hg > fc-pcm-if
comparison fpga/tools/yosys-wrap @ 0:4624f3da093a
starting project with FPGA infra from fc-sim-sniff
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Fri, 11 Oct 2024 18:36:25 +0000 |
| parents | |
| children |
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| -1:000000000000 | 0:4624f3da093a |
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| 1 #!/bin/sh | |
| 2 | |
| 3 if [ $# -lt 3 ] | |
| 4 then | |
| 5 echo "usage: $0 top-module json-output verilog-src..." 1>&2 | |
| 6 exit 1 | |
| 7 fi | |
| 8 | |
| 9 top="$1" | |
| 10 json="$2" | |
| 11 | |
| 12 shift | |
| 13 shift | |
| 14 | |
| 15 rm -f "$json" | |
| 16 yosys -p "synth_ice40 -top $top -json $json" "$@" | |
| 17 | |
| 18 if [ -f "$json" ] | |
| 19 then | |
| 20 echo "$json created, declaring success" | |
| 21 exit 0 | |
| 22 else | |
| 23 echo "$json NOT created, declaring error" | |
| 24 exit 1 | |
| 25 fi |