# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1502011317 0
# Node ID f5c10ec9c5fd7f1d63272f47a1876dadea625d8c
# Parent  f62b71017afdcde60985acd2f63fedb83ce7e418
init.c: module passes compilation,
Init_Drivers() and Init_Serial_Flows() functions are good,
Init_Target() and Init_Unmask_IT() need further work

diff -r f62b71017afd -r f5c10ec9c5fd src/cs/system/Main/init.c
--- a/src/cs/system/Main/init.c	Sun Aug 06 08:57:26 2017 +0000
+++ b/src/cs/system/Main/init.c	Sun Aug 06 09:21:57 2017 +0000
@@ -298,22 +298,6 @@
  */
 void Init_Target(void)
 {
-
-	
-  #if (BOARD==70)|| (BOARD==71)
-  /* Variable for reading the BCR for MCP RAM */
-  unsigned short bcrTmpVal;
-  #endif
- (*(volatile Uint16 *) 0xFFFF702A) = 0x0002;//reset the UART module.
-#if (CHIPSET == 15)
-        char detect_code[80];
-        typedef void (*pf_t)(UWORD32, UWORD16 *, UWORD16 *);
-	extern void ffsdrv_device_id_read(UWORD32 base_addr, UWORD16 *manufact, UWORD16 *device);
-        pf_t myfp;
-	UWORD16 manufact;
-        UWORD16 device_id[3];
-
-#endif
   #if (BOARD == 5)
     #define WS_ROM  (1)
     #define WS_RAM  (1)
@@ -583,18 +567,6 @@
       #endif   /* (CHIPSET == 15) */
 
 
-      /*
-       * Initialize current DSP clock to 0 in order to pass through
-       * the right DSP latency configuration (increase DSP clock)
-       * in f_dynamic_clock_cfg().
-       * Obviously, the real DSP clock is not 0kHz.
-       * d_dsp_cur_clk will be updated after clock configuration in f_dynamic_clock_cfg().
-       */
-      d_dsp_cur_clk = 0;   // Used to keep track of current DSP clock.
-
-      /* Dynamic clock configuration */
-      f_dynamic_clock_cfg(C_CLOCK_CFG_DEFAULT);
-
       // Write_en_0 = 0 , Write_en_1 = 0
       RHEA_INITARM(0,0);