# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1502043854 0
# Node ID e18367b5427ec57c5378798702951182c0319a15
# Parent  d5a34ea92f2a0ce9e1c4b1cf11c23c54a9b07ab0
init.c: applied our necessary FreeCalypso changes to reconstructed Init_Target()

diff -r d5a34ea92f2a -r e18367b5427e src/cs/system/Main/init.c
--- a/src/cs/system/Main/init.c	Sun Aug 06 17:58:13 2017 +0000
+++ b/src/cs/system/Main/init.c	Sun Aug 06 18:24:14 2017 +0000
@@ -17,6 +17,7 @@
   #include "chipset.cfg"
   #include "board.cfg"
   #include "swconfig.cfg"
+  #include "fc-target.cfg"
   #if (OP_L1_STANDALONE == 0)
     #include "rv.cfg"
     #include "sys.cfg"
@@ -372,6 +373,8 @@
         #else
           #if (BOARD==35)
             *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x2000;
+          #elif defined(CONFIG_TARGET_PIRELLI)	/* from disasm of original fw */
+            *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x6050;
           #else
             *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x6000;
           #endif   /* (BOARD == 35) */
@@ -502,11 +505,44 @@
       DPLL_INIT_BYPASS_MODE(DPLL_BYPASS_DIV_1);
       DPLL_INIT_DPLL_CLOCK(DPLL_LOCK_DIV_1, 8);
       CLKM_InitARMClock(0x00, 2, 0); /* no low freq, no ext clock, div by 1 */
-      MEM_INIT_CS0(3, MEM_DVS_16, MEM_WRITE_EN, 0);
-      MEM_INIT_CS1(3, MEM_DVS_16, MEM_WRITE_EN, 0);
-      MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0);
-      MEM_INIT_CS3(3, MEM_DVS_16, MEM_WRITE_EN, 0);
-      MEM_INIT_CS4(0, MEM_DVS_8,  MEM_WRITE_EN, 0);
+      /*
+       * FreeCalypso change: memory timings and widths
+       * are target-dependent.
+       */
+      #ifdef CONFIG_TARGET_PIRELLI
+        /*
+         * Pirelli's version of this Init_Target() function
+         * in their fw does the following:
+         */
+        MEM_INIT_CS0(4, MEM_DVS_16, MEM_WRITE_EN, 0);
+        MEM_INIT_CS1(4, MEM_DVS_16, MEM_WRITE_EN, 0);
+        MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0);
+        MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0);
+        MEM_INIT_CS4(7, MEM_DVS_16, MEM_WRITE_EN, 0);
+      #elif defined(CONFIG_TARGET_FCFAM)
+        /*
+         * The settings currently adopted for the FreeCalypso
+         * hardware family, only nCS0, nCS1 and nCS2 are used
+         * presently.
+         */
+        MEM_INIT_CS0(4, MEM_DVS_16, MEM_WRITE_EN, 0);
+        MEM_INIT_CS1(4, MEM_DVS_16, MEM_WRITE_EN, 0);
+        MEM_INIT_CS2(4, MEM_DVS_16, MEM_WRITE_EN, 0);
+        MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0);
+        MEM_INIT_CS4(4, MEM_DVS_16, MEM_WRITE_EN, 0);
+      #else
+        /*
+         * The original settings from Openmoko,
+         * only nCS0 and nCS1 are actually used,
+         * same as on Mot C1xx phones,
+         * the nCS2/3/4 settings are dummies from TI.
+         */
+        MEM_INIT_CS0(3, MEM_DVS_16, MEM_WRITE_EN, 0);
+        MEM_INIT_CS1(3, MEM_DVS_16, MEM_WRITE_EN, 0);
+        MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0);
+        MEM_INIT_CS3(3, MEM_DVS_16, MEM_WRITE_EN, 0);
+        MEM_INIT_CS4(0, MEM_DVS_8,  MEM_WRITE_EN, 0);
+      #endif
       MEM_INIT_CS6(0, MEM_DVS_32, MEM_WRITE_EN, 0);
       MEM_INIT_CS7(0, MEM_DVS_32, MEM_WRITE_DIS, 0);
       RHEA_INITAPI(0,1);
@@ -711,7 +747,14 @@
         #endif
 
         // set the debug latch to 0x0000.
- 	    *((volatile SYS_UWORD16 *) 0x2700000) = 0x0000;
+        /*
+         * FreeCalypso change: this write is only correct when running
+         * on an actual D-Sample board, but not on any of the real-world
+         * Calypso target devices.
+         */
+        #if 0
+          *((volatile SYS_UWORD16 *) 0x2700000) = 0x0000;
+        #endif
       #endif // BOARD
 
       // Enable HW Timers 1 & 2