# HG changeset patch # User Mychaela Falconia # Date 1502039299 0 # Node ID a498108254c90116cbf7e0275f06079a90502e44 # Parent f5c10ec9c5fd7f1d63272f47a1876dadea625d8c init.c: Init_Target() reconstructed, perfect match to original object diff -r f5c10ec9c5fd -r a498108254c9 src/cs/system/Main/init.c --- a/src/cs/system/Main/init.c Sun Aug 06 09:21:57 2017 +0000 +++ b/src/cs/system/Main/init.c Sun Aug 06 17:08:19 2017 +0000 @@ -490,24 +490,30 @@ #endif #endif - #if (CHIPSET ==15) - //Enable APLL - *((volatile unsigned short *) (C_MAP_CLKM_BASE+0x10)) = 0x01|0x6; - // UART Clock from APLL - *((volatile unsigned short *) CLKM_CNTL_CLK_PROG_FREE_RUNN) = 0x0001; - (*(volatile Uint16 *) 0xFFFF702A) = 0x0002;//reset the UART module. - - #endif - - - - // // Control HOM/SAM automatic switching //-------------------------------------------------- *((volatile unsigned short *) CLKM_CNTL_CLK) &= ~CLKM_EN_IDLE3_FLG; /* + * The following part has been reconstructed from disassembly. + */ + RHEA_INITRHEA(0,0,0xFF); + DPLL_INIT_BYPASS_MODE(DPLL_BYPASS_DIV_1); + DPLL_INIT_DPLL_CLOCK(DPLL_LOCK_DIV_1, 8); + CLKM_InitARMClock(0x00, 2, 0); /* no low freq, no ext clock, div by 1 */ + MEM_INIT_CS0(3, MEM_DVS_16, MEM_WRITE_EN, 0); + MEM_INIT_CS1(3, MEM_DVS_16, MEM_WRITE_EN, 0); + MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0); + MEM_INIT_CS3(3, MEM_DVS_16, MEM_WRITE_EN, 0); + MEM_INIT_CS4(0, MEM_DVS_8, MEM_WRITE_EN, 0); + MEM_INIT_CS6(0, MEM_DVS_32, MEM_WRITE_EN, 0); + MEM_INIT_CS7(0, MEM_DVS_32, MEM_WRITE_DIS, 0); + RHEA_INITAPI(0,1); + RHEA_INITARM(0,0); + DPLL_SET_PLL_ENABLE; + + /* * Disable and Clear all pending interrupts */ #if (CHIPSET == 12) || (CHIPSET == 15) @@ -518,68 +524,12 @@ F_INTH_RESET_ALL_IT; // reset all IRQ/FIQ source #else INTH_DISABLEALLIT; - INTH_RESETALLIT; + #if 0 /* not present in our reference binary object */ + INTH_RESETALLIT; + #endif INTH_CLEAR; /* reset IRQ/FIQ source */ #endif - #if (CHIPSET == 12) - /* API-RHEA control register configuration */ - f_memif_init_api_rhea_ctrl(C_MEMIF_API_RHEA_ADAPT, - C_MEMIF_API_RHEA_ADAPT, - C_MEMIF_API_RHEA_ADAPT, - C_MEMIF_API_RHEA_NO_DEBUG); - - #if ((BOARD == 43) || (BOARD == 45)) - // if Esample,Evaconso active extended page mode - // With Calypso+ chipset, extended page mode can be enabled - // only if W_A_CALYPSO_PLUS_SPR_19599 is set to one in l1_confg.h. - // see L1_MCU-SPR-17515 and L1_MCU-SPR-19599 for more information - f_memif_extended_page_mode_enable(); - #endif - #endif /* (CHIPSET == 12) */ - - #if (CHIPSET == 15) - /* API-RHEA control register configuration */ - f_emif_api_rhea_conf(C_RHEA_STROBE0_ACCESS_SIZE_ADAPT_ENABLE, - C_RHEA_STROBE1_ACCESS_SIZE_ADAPT_ENABLE, - C_API_ACCESS_SIZE_ADAPT_ENABLE, - C_ARM_DEBUG_DISABLE); - #if (BOARD == 70) || (BOARD == 71) - // set the EMIF settings here for locosto - // We could have the default settings here and - // then change it after dynamic clock config - /* MCP RAM Setting Is being done here */ -#if 0 /* This is commented out by Ranga */ - #if (PSP_FAILSAFE!=1) - bcrTmpVal = *((volatile unsigned char *)0x007FFFFFE); - bcrTmpVal +=1; - bcrTmpVal = *((volatile unsigned char *)0x007FFFFFE); - *((volatile unsigned char *)0x007FFFFFE)=0x0001; - *((volatile unsigned char *)0x007FFFFFE)=0x1542; - - /* Setting NOR Flash to these 3 Wait State */ - *((volatile char *)0x06000AAA)=0xAA; - *((volatile char *)0x06000555)=0x55; - *((volatile char *)0x06016AAA)=0xC0; - #endif -#endif - #endif - #endif /* (CHIPSET == 15) */ - - - // Write_en_0 = 0 , Write_en_1 = 0 - RHEA_INITARM(0,0); - - #if (CHIPSET ==15) - // Mark USB on 52 MHZ Clock - *((volatile unsigned short *) (CLKM_CNTL_CLK_USB)) = 0x02; - #endif - - #if (CHIPSET == 12) || ((CHIPSET == 10) && (OP_WCP == 1)) - /* Allocate the 0.5 Mbits Shared RAM to the DSP */ - f_memif_shared_sram_allocation(C_MEMIF_DSPMS_0_5MBITS_TO_DSP); - #endif - // INTH //-------------------------------------------------- #if (CHIPSET == 12) || (CHIPSET == 15) @@ -693,20 +643,6 @@ *((volatile SYS_UWORD16 *)ULPD_SETUP_RF_REG) = SETUP_RF; // 31 periods #endif - #if (CHIPSET == 15) - *((volatile SYS_UWORD16 *)ULPD_DCXO_SETUP_SLEEPN) = SETUP_SLEEPZ; // 0 - *((volatile SYS_UWORD16 *)ULPD_DCXO_SETUP_SYSCLKEN) = SETUP_SYSCLKEN; // 255 clocks of 32 KHz for 7.8 ms DCXO delay for Locosto - *((volatile SYS_UWORD16 *)0xFFFEF192) = 0x1; //CLRZ - *((volatile SYS_UWORD16 *)0xFFFEF190) = 0x2; //SLPZ - *((volatile SYS_UWORD16 *)0xFFFEF18E)= 0x2; //SYSCLKEN - *((volatile SYS_UWORD16 *)0xFFFEF186) = 0x2; //CLK13_EN - *((volatile SYS_UWORD16 *)0xFFFEF18A) = 0x2; //DRP_DBB_SYSCLK - - - - - #endif - // Set Gauging versus HF (PLL) //================================================= ULDP_GAUGING_SET_HF; // Enable gauging versus HF @@ -776,186 +712,15 @@ // set the debug latch to 0x0000. *((volatile SYS_UWORD16 *) 0x2700000) = 0x0000; - #elif ((BOARD == 70) || (BOARD == 71)) - AI_InitIOConfig(); - /* Mark The System configuration According to I-Sample */ - /* Adding GPIO Mux Setting Here */ - pin_configuration_all(); // Init Tuned for Power Management - /* A22 is Enabled in int.s hence not Here */ - /* FIXME: PULL_UP Enable and PULL UP Values Need to revisited */ - - /* Add code to find out the manufacture id of NOR flash*/ - - // Copy ffsdrv_device_id_read() function code to RAM. The only known - // way to determine the size of the code is to look either in the - // linker-generated map file or in the assember output file. - ffsdrv_copy_code_to_ram((UWORD16 *) detect_code, - (UWORD16 *) &ffsdrv_device_id_read, - sizeof(detect_code)); - - // Combine bit 0 of the thumb mode function pointer with the address - // of the code in RAM. Then call the detect function in RAM. - myfp = (pf_t) (((int) &ffsdrv_device_id_read & 1) | (int) detect_code); - (*myfp)(0x06000000, &manufact, device_id); - - enable_ps_ram_burst(); - - if( 0x7e == device_id[0] ) - { - enable_flash_burst(); - flash_device_id = 0x7E; - } - else - { - enable_flash_burst_mirror(); - flash_device_id = 0; - } - - - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - -#if 0 // Init Changed for tuning to Power Management -Old Init Commented - /* Ball N9 Mapped to TSPACT_8 (TPU) */ - F_IO_CONFIG(C_CONF_GPIO_5,C_CONF_PUPD_EN|0x01); - /* Ball A6 ND_WE */ - F_IO_CONFIG(C_CONF_GPIO_18,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01); - /* Ball C2 ND_RDY */ - F_IO_CONFIG(C_CONF_GPIO_34,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01); - /* Ball C3 ND_RE */ - F_IO_CONFIG(C_CONF_GPIO_31,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01); - /* BALL E5 CAM_D_4 */ - F_IO_CONFIG(C_CONF_ND_NWP,0x02); - /* BALL F6 ND_CLE */ - F_IO_CONFIG(C_CONF_GPIO_32,C_CONF_PUPD_EN|0x01); - /* BALL H8 ND_ALE */ - F_IO_CONFIG(C_CONF_GPIO_33,C_CONF_PUPD_EN|0x01); - /* BALL E10 LCD_NCS0 */ - F_IO_CONFIG(C_CONF_GPIO_13,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01); - /* BALL C11 GPIO_10 */ - F_IO_CONFIG(C_CONF_GPIO_10,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01); - /* BALL D10 GPIO_11 */ - F_IO_CONFIG(C_CONF_GPIO_11,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01); - /* BALL M6 CAM_D_1 */ - F_IO_CONFIG(C_CONF_GPIO_0,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x02); - /* BALL N5 CAM_D_0 */ - F_IO_CONFIG(C_CONF_GPIO_47,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x02); - /* BALL A5 CAM_LCLK */ - F_IO_CONFIG(C_CONF_GPIO_21,0x01); - /* BALL C6 CAM_XCLK */ - F_IO_CONFIG(C_CONF_GPIO_22,0x01); - /* BALL E7 CAM_VS */ - F_IO_CONFIG(C_CONF_GPIO_20,0x01); - /* BALL F8 CAM_HS */ - F_IO_CONFIG(C_CONF_GPIO_19,0x01); - /* BALL K7 MCSI_TX */ - F_IO_CONFIG(C_CONF_GPIO_45,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01); - /* BALL M5 MCSI_FS */ - F_IO_CONFIG(C_CONF_GPIO_44,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01); - /* BALL N3 MCSI_CK */ - F_IO_CONFIG(C_CONF_GPIO_43,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01); - /* BALL P2 MCSI_RX */ - F_IO_CONFIG(C_CONF_GPIO_46,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01); - /* BALL B11 TSPACT_10 */ - F_IO_CONFIG(C_CONF_GPIO_12,C_CONF_PUPD_EN|0x01); - /* BALL B3 CAM_D_5 */ - F_IO_CONFIG(C_CONF_GPIO_30,C_CONF_PUPD_EN|0x03); - /* BALL C4 CAM_D_7 */ - F_IO_CONFIG(C_CONF_GPIO_28,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x03); - /* BALL C5 SPI_DATA_MOSI */ - F_IO_CONFIG(C_CONF_GPIO_25,C_CONF_PUPD_EN|0x01); - /* BALL E6 SPI_NCS0 */ - F_IO_CONFIG(C_CONF_GPIO_26,C_CONF_PUPD_EN|0x01); - /* BALL F7 SPI_DATA_MIS0 */ - F_IO_CONFIG(C_CONF_GPIO_24,C_CONF_PUPD_EN|0x03); - /* BALL G6 CAM_D_2 */ - F_IO_CONFIG(C_CONF_GPIO_7,C_CONF_PUPD_EN|0x05); - /* BALL G7 CAM_D_6 */ - F_IO_CONFIG(C_CONF_GPIO_29,C_CONF_PUPD_EN|0x03); - /* BALL G8 SPI_NCS1 */ - F_IO_CONFIG(C_CONF_GPIO_27,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01); - /* BALL G9 SPI_CLK */ - F_IO_CONFIG(C_CONF_GPIO_23,C_CONF_PUPD_EN|0x01); - /* BALL L6 CKM */ - F_IO_CONFIG(C_CONF_GPIO_42,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01); - - /*By default the muxed bus is given to LCD*/ - C_CONF_LCD_CAM_NAN_REG=0x03; - -#endif // for #if 0 Init Changed for Power Management #endif // BOARD // Enable HW Timers 1 & 2 TM_EnableTimer (1); TM_EnableTimer (2); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); #endif /* (OP_L1_STANDALONE == 0) */ #endif /* #if (BOARD == 5) */ -#if(OP_L1_STANDALONE == 1 && MIRROR_BIT == 1 ) //temp FIX for L1 standalone-this fix will work only for I-sample mirror bit -//#if(OP_L1_STANDALONE == 1 ) - //AI_InitIOConfig(); - //pin_configuration_all(); // Init Tuned for Power Management - //enable_ps_ram_burst(); - //enable_flash_burst_mirror(); - flash_device_id = 0; - //asm(" NOP"); - //asm(" NOP"); - //asm(" NOP"); - //asm(" NOP"); - //asm(" NOP"); - //asm(" NOP"); - //asm(" NOP"); - //asm(" NOP"); -#elif(OP_L1_STANDALONE == 1 && MIRROR_BIT == 0 ) - flash_device_id = 0x7E; -#endif - - - #if GSM_IDLE_RAM_DEBUG - #if (CHIPSET!=15) - *((volatile SYS_UWORD16 *) 0xFFFE4806) = (0x0020); - AI_ConfigBitAsOutput(3); - AI_ConfigBitAsOutput(2); - #endif - #endif - #if (CHIPSET==15) - { - volatile unsigned int * configReg=(volatile unsigned int *)0xFFFEF01C; - *configReg &= 0xF7FF; - } - #endif - } /*