# HG changeset patch # User Mychaela Falconia # Date 1529481212 0 # Node ID 15c61c8f3166c93ef4c9f26b0fb8a8cdb6fa9fdf # Parent ad7f986afae384b0f196e1177317c3a2e8b90774 doc/FCDEV3B-hardware-bug: update on the investigation and the proposed fix diff -r ad7f986afae3 -r 15c61c8f3166 doc/FCDEV3B-hardware-bug --- a/doc/FCDEV3B-hardware-bug Tue Jun 19 17:03:34 2018 +0000 +++ b/doc/FCDEV3B-hardware-bug Wed Jun 20 07:53:32 2018 +0000 @@ -17,12 +17,17 @@ * On all of the boards there is a problem with sleep modes: when the firmware is running from flash as opposed to RAM, certain sleep-wake sequences cause - an erratic self-reboot or a hang. It is suspected (though not proven yet) - that the FDP output goes low during all sleep modes, our Spansion flash chip - gets unhappy with the reset timing it gets subjected to, and some flash reads - (instruction fetches) don't work after wakeup. So far the only workable + an erratic self-reboot or a hang. Oscilloscope probing on a decased Pirelli + DP-L10 motherboard on which Calypso's FDP output is accessible seems to + confirm my (Mychaela's) suspicion that this FDP signal goes low during all + sleep modes, and the current working hypothesis is that our Spansion flash + chip gets unhappy with the reset timing it gets subjected to, and some flash + reads (instruction fetches) don't work after wakeup. So far the only workable solution has been to disable all sleep modes in all FCDEV3B fw builds; - nothing else has been successful. + nothing else has been successful. However, re-enabling all of these sleep + modes with AT%SLEEP=4 works fine when the firmware image executes out of RAM + instead of flash, further supporting our current working hypothesis as to the + root cause. The fcdev3b-hacks directory contains two hacks that can be applied to FCDEV3B firmware images (fwimage.bin builds) as xxd binary patches: @@ -43,7 +48,13 @@ interface with AT+CFUN=1 in the l1reconst config when running from flash with small sleep enabled still triggers erratic misbehaviour even with this patch. -The proper fix will be to change the PCB to not connect the flash chip's reset -input to FDP any more, and connect it to a pull-up resistor instead. But this -fix will require an expensive PCB respin, hence some experiments to test this -idea will need to be done first. +The proper fix will require a new PCB spin to change the flash reset wiring: +instead of driving it with Calypso's FDP output, use the ON_nOFF master reset +signal from Iota's VRPC block, fed through a logic voltage level translating +buffer to change it from 1.5 V to 2.8 V logic. The flash chip we are using has +lower power consumption when it is NOT held in reset, hence unlike TI's intent +with FDP, we don't want our flash chip to go into reset during any sleep at all. + +The new PCB revision with this change is now in the process of being finalized, +and we will soon need the funding to produce the new boards. Anyone who is +interested in helping to make FCDEV3B V2 a reality should email Mychaela.