# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1560796832 0
# Node ID 07d0dc4431f4575601325939ac9308a094338890
# Parent  a7ed7d4483b07e1acd073082cf8b81e0b7cec866
bootloader.s: same MEMIF fix as in int.s plus DPLL BYPASS fix

Both MEMIF and DPLL settings are now the same between int.s and bootloader.s
assembly code paths.  Previously bootloader.s was setting DPLL BYPASS /2 mode,
which persisted until _INT_Initialize code with the bootloader body omitted,
or was changed to /1 in the hardware init function in the
bootloader.lib:start.obj module.

diff -r a7ed7d4483b0 -r 07d0dc4431f4 components/bootloader
--- a/components/bootloader	Mon Jun 17 02:11:17 2019 +0000
+++ b/components/bootloader	Mon Jun 17 18:40:32 2019 +0000
@@ -17,6 +17,13 @@
 ASMFLAGS="$ASMFLAGS -dOP_WCP=0"
 ASMFLAGS="$ASMFLAGS -dWCP_PROF=0"
 
+if [ "$RF" = 12 ]
+then
+	ASMFLAGS="$ASMFLAGS -dVCXO_26MHZ=1"
+else
+	ASMFLAGS="$ASMFLAGS -dVCXO_26MHZ=0"
+fi
+
 asm_file $SRCDIR/bootloader.s
 
 ASMFLAGS="-mt -me"
diff -r a7ed7d4483b0 -r 07d0dc4431f4 src/cs/system/bootloader/src/bootloader.s
--- a/src/cs/system/bootloader/src/bootloader.s	Mon Jun 17 02:11:17 2019 +0000
+++ b/src/cs/system/bootloader/src/bootloader.s	Mon Jun 17 18:40:32 2019 +0000
@@ -161,9 +161,19 @@
             .endif
 
           .elseif   BOARD = 41       ; D-Sample FLASH CS0
+
+; FreeCalypso change, please see MEMIF-wait-states document
+; in the freecalypso-docs repository for the explanation.
+
+    .if VCXO_26MHZ = 1
+CS0_MEM_REG   .short  0x2a2  ; 1 Dummy Cycle 16 bit 2 WS SW BP enable
+CS1_MEM_REG   .short  0x2a2  ; 1 Dummy Cycle 16 bit 2 WS SW BP enable
+CS2_MEM_REG   .short  0x2a2  ; 1 Dummy Cycle 16 bit 2 WS SW BP enable
+    .else
 CS0_MEM_REG   .short  0x2a1  ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
 CS1_MEM_REG   .short  0x2a1  ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
 CS2_MEM_REG   .short  0x2a1  ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
+    .endif
 CS3_MEM_REG   .short  0x283  ; 1 Dummy Cycle  8 bit 3 WS SW BP enable
 CS4_MEM_REG   .short  0x281  ; 1 Dummy Cycle  8 bit 1 WS SW BP enable
 
@@ -252,7 +262,7 @@
 
 CNTL_ARM_CLK_RST  .short  0x1081	   ; Initialization of CNTL_ARM_CLK register
                                      ; Use DPLL, Divide by 1
-DPLL_CONTROL_RST  .short  0x2006     ; Configure DPLL in default state
+DPLL_CONTROL_RST  .short  0x2002     ; Configure DPLL in BYPASS mode, /1
 DISABLE_DU_MASK   .short  0x0800     ; Mask to Disable the DU module
 MPU_CTL_RST       .short  0x0000     ; Reset value of MPU_CTL register - All protections disabled
 
@@ -264,7 +274,7 @@
 
 CNTL_ARM_CLK_RST  .short  0x1081	   ; Initialization of CNTL_ARM_CLK register
                                      ; Use DPLL, Divide by 1
-DPLL_CONTROL_RST  .short  0x2006     ; Configure DPLL in default state
+DPLL_CONTROL_RST  .short  0x2002     ; Configure DPLL in BYPASS mode, /1
 DISABLE_DU_MASK   .short  0x0800     ; Mask to Disable the DU module
 MPU_CTL_RST       .short  0x0000     ; Reset value of MPU_CTL register - All protections disabled
 
@@ -276,7 +286,7 @@
 
 CNTL_ARM_CLK_RST  .short  0x1081	   ; Initialization of CNTL_ARM_CLK register
                                      ; Use DPLL, Divide by 1
-DPLL_CONTROL_RST  .short  0x2006     ; Configure DPLL in default state
+DPLL_CONTROL_RST  .short  0x2002     ; Configure DPLL in BYPASS mode, /1
 DISABLE_DU_MASK   .short  0x0800     ; Mask to Disable the DU module
 MPU_CTL_RST       .short  0x0000     ; Reset value of MPU_CTL register - All protections disabled
 
@@ -672,4 +682,4 @@
     .word   end
 
         .end
-        
\ No newline at end of file
+