FreeCalypso > hg > fc-magnetite
view src/cs/system/main/init.asm @ 600:8f50b202e81f
board preprocessor conditionals: prep for more FC hw in the future
This change eliminates the CONFIG_TARGET_FCDEV3B preprocessor symbol and
all preprocessor conditionals throughout the code base that tested for it,
replacing them with CONFIG_TARGET_FCFAM or CONFIG_TARGET_FCMODEM. These
new symbols are specified as follows:
CONFIG_TARGET_FCFAM is intended to cover all hardware designs created by
Mother Mychaela under the FreeCalypso trademark. This family will include
modem products (repackagings of the FCDEV3B, possibly with RFFE or even
RF transceiver changes), and also my desired FreeCalypso handset product.
CONFIG_TARGET_FCMODEM is intended to cover all FreeCalypso modem products
(which will be firmware-compatible with the FCDEV3B if they use TI Rita
transceiver, or will require a different fw build if we switch to one of
Silabs Aero transceivers), but not the handset product. Right now this
CONFIG_TARGET_FCMODEM preprocessor symbol is used to conditionalize
everything dealing with MCSI.
At the present moment the future of FC hardware evolution is still unknown:
it is not known whether we will ever have any beyond-FCDEV3B hardware at all
(contingent on uncertain funding), and if we do produce further FC hardware
designs, it is not known whether they will retain the same FIC modem core
(triband), if we are going to have a quadband design that still retains the
classic Rita transceiver, or if we are going to switch to Silabs Aero II
or some other transceiver. If we produce a quadband modem that still uses
Rita, it will run exactly the same fw as the FCDEV3B thanks to the way we
define TSPACT signals for the RF_FAM=12 && CONFIG_TARGET_FCFAM combination,
and the current fcdev3b build target will be renamed to fcmodem. OTOH, if
that putative quadband modem will be Aero-based, then it will require a
different fw build target, the fcdev3b target will stay as it is, and the
two targets will both define CONFIG_TARGET_FCFAM and CONFIG_TARGET_FCMODEM,
but will have different RF_FAM numbers. But no matter which way we are
going to evolve, it is not right to have conditionals on CONFIG_TARGET_FCDEV3B
in places like ACI, and the present change clears the way for future
evolution.
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Mon, 01 Apr 2019 01:05:24 +0000 |
| parents | 838eeafb0051 |
| children | a7ed7d4483b0 |
line wrap: on
line source
;****************************************************************************** ; TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION ; ; Property of Texas Instruments -- For Unrestricted Internal Use Only ; Unauthorized reproduction and/or distribution is strictly prohibited. This ; product is protected under copyright law and trade secret law as an ; unpublished work. Created 1987, (C) Copyright 1996 Texas Instruments. All ; rights reserved. ; ; ; Filename : init.asm ; ; Description : Environment configuration ; ; Project : drivers ; ; Author : pmonteil@tif.ti.com Patrice Monteil. ; ; Version number : 1.4 ; ; Date and time : 03/06/01 10:44:19 ; ; Previous delta : 12/19/00 14:28:47 ; ; SCCS file : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/mod/emu_p/EMU_P_C_SAMPLE_REQ1145_BIS/drivers1/board_7/SCCS/s.init.asm ; ; Sccs Id (SID) : '@(#) init.asm 1.4 03/06/01 10:44:19 ' ; ; ;***************************************************************************** ; use in int.s for first initializations .if BOARD = 6 .if CHIPSET != 12 CS0_MEM_REG .short 0x2A0 ;ROM init : 0 WS, 16 bits, little CS1_MEM_REG .short 0x281 ;RAM init : 1 WS, 8 bits, little CS2_MEM_REG .short 0x2A1 ;RAM init : 1 WS, 16 bits, little CS3_MEM_REG .short 0x283 ;RAM init : 5 WS, 8 bits, little CS4_MEM_REG .short 0xe85 ;RAM init : 5 WS, 8 bits, little .endif .if CHIPSET = 3 CS6_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable .elseif CHIPSET = 4 CS6_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable CS7_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable .elseif CHIPSET = 5 CS6_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable .elseif CHIPSET = 6 CS6_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable .elseif CHIPSET = 7 CS6_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable CS7_MEM_REG .short 0x040 ;Internal BOOT ROM init : 0 WS, 32 bits, little, write disable .elseif CHIPSET = 8 CS6_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable CS7_MEM_REG .short 0x040 ;Internal BOOT ROM init : 0 WS, 32 bits, little, write disable .elseif CHIPSET = 10 CS6_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable CS7_MEM_REG .short 0x040 ;Internal BOOT ROM init : 0 WS, 32 bits, little, write disable .elseif CHIPSET = 11 CS6_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable CS7_MEM_REG .short 0x040 ;Internal BOOT ROM init : 0 WS, 32 bits, little, write disable .elseif CHIPSET = 12 CS0_MEM_REG .short 0x2A1 ;CALYPSO PLUS TEST MODE - TO BE ERASED - RAM init : 1 WS, 16 bits, little CS4_MEM_REG .short 0x2A1 ;RAM init : 1 WS, 16 bits, little CS5_MEM_REG .short 0x2A1 ;ROM init : 0 WS, 16 bits, little .endif ; CHIPSET = 3, 4, 5, 6, 7, 8, 10 or 11 or 12 .elseif BOARD = 7 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable .if OP_WCP = 1 CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 0 WS SW BP enable .else CS1_MEM_REG .short 0x2a0 ; 1 Dummy Cycle 16 bit 0 WS SW BP enable .endif CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable CS4_MEM_REG .short 0x281 ; 1 Dummy Cycle 8 bit 1 WS SW BP enable .if CHIPSET = 3 CS6_MEM_REG .short 0x2c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable .elseif CHIPSET = 4 CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable CS7_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable .elseif CHIPSET = 5 CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable .elseif CHIPSET = 6 .if OP_WCP = 1 CS6_MEM_REG .short 0x2c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable .else CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable .endif .endif ; CHIPSET = 3, 4, 5 or 6 .elseif BOARD = 8 CS0_MEM_REG .short 0x2a0 ; 1 Dummy Cycle 16 bit 0 WS SW BP enable CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable CS4_MEM_REG .short 0xe85 ; default reset value .if CHIPSET = 4 CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable CS7_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable .elseif CHIPSET = 7 CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable .elseif CHIPSET = 8 CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable .endif ; CHIPSET = 4, 7 or 8 .elseif BOARD = 9 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable CS4_MEM_REG .short 0xe85 ; default reset value .if CHIPSET = 4 CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable CS7_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable .elseif CHIPSET = 7 CS6_MEM_REG .short 0x2c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable .elseif CHIPSET = 8 CS6_MEM_REG .short 0x2c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable .endif ; CHIPSET = 4, 7 or 8 .elseif BOARD = 35 CS0_MEM_REG .short 0x7C0 ; 7 WS, 32 bits, write enabled CS1_MEM_REG .short 0x7C0 ; 7 WS, 32 bits, write enabled CS2_MEM_REG .short 0x7C0 ; 7 WS, 32 bits, write enabled CS6_MEM_REG .short 0x7C0 ; 7 WS, 32 bits, write enabled CS7_MEM_REG .short 0x7C0 ; 7 WS, 32 bits, write enabled API_ADAPT .equ 0x6A CS7_SIZE .equ 0x2000 ; 8 kB CS7_ADDR .equ 0x03800000 ; Initial address before toggling nIBOOT SRAM_ADDR .equ 0x00800000 ; Internal SRAM start address SRAM_SIZE .equ 0x00050000 ; 2.5 MBits armio_in .word 0xFFFE4800 ; ARMIO_IN register address armio_out .word 0xFFFE4802 ; ARMIO_OUT register address addrExtraConf .word 0xFFFFFB10 ; Extra configuration addrCS7 .word 0xFFFFFB08 ; CS7 configuration DEF_EXTRA_CONF .short 0x033E ; Default configuration EXTRA_CONF .short 0x013E ; Boot configuration .elseif BOARD = 40 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 0 WS SW BP enable CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable CS4_MEM_REG .short 0xe85 ; default reset value .if CHIPSET = 8 CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable .elseif CHIPSET = 10 CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable .elseif CHIPSET = 11 CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable .endif ; CHIPSET = 8, 10 or 11 .elseif BOARD = 41 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable CS4_MEM_REG .short 0xe85 ; default reset value .if CHIPSET = 8 CS6_MEM_REG .short 0x2c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable .elseif CHIPSET = 10 CS6_MEM_REG .short 0x2c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable .elseif CHIPSET = 11 CS6_MEM_REG .short 0x2c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable .endif ; CHIPSET = 8, 10 or 11 .elseif BOARD = 43 .if CHIPSET = 12 CS0_MEM_REG .short 0x2A0 ;CALYPSO PLUS TEST MODE - TO BE ERASED BOARD 43 init.asm - RAM init : 1 WS, 16 bits, little CS4_MEM_REG .short 0x2A1 ;RAM init : 1 WS, 16 bits, little CS5_MEM_REG .short 0x2A0 ;ROM init : 0 WS, 16 bits, little .endif ; CHIPSET = 12 .elseif BOARD = 45 .if CHIPSET = 12 CS0_MEM_REG .short 0x2A1 ;CALYPSO PLUS TEST MODE - TO BE ERASED BOARD 43 init.asm - RAM init : 1 WS, 16 bits, little CS4_MEM_REG .short 0x2A1 ;RAM init : 1 WS, 16 bits, little CS5_MEM_REG .short 0x2A1 ; init : 0 WS, 16 bits, little .endif ; CHIPSET = 12 .endif ; BOARD CLKM_MEM_REG .equ 0x31 ;the same define INIT_CLKM_ARM_CLK = 0x1031 for InitArmAfterReset CTL_MEM_REG .short 0x02a ; rhea strobe 0/1 + API access size adaptation