view fcdev3b-hacks/src/romvecs-insert.S @ 605:07d0dc4431f4

bootloader.s: same MEMIF fix as in int.s plus DPLL BYPASS fix Both MEMIF and DPLL settings are now the same between int.s and bootloader.s assembly code paths. Previously bootloader.s was setting DPLL BYPASS /2 mode, which persisted until _INT_Initialize code with the bootloader body omitted, or was changed to /1 in the hardware init function in the bootloader.lib:start.obj module.
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 17 Jun 2019 18:40:32 +0000
parents 8d9298e0823a
children
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	.text
	.code	32
	.globl	_entry

_entry:	adr	r0, vectors
	ldmia	r0, {r1-r7}
	mov	r0, #0x800000
	stmia	r0, {r1-r7}
	ldr	pc, jumpaddr

vectors:
	.word	0x4000
	.word	0x4004
	.word	0x4008
	.word	0x400C
	.word	0x4010
	.word	0x4014
	.word	0x4018
jumpaddr:
	.word	0x4058