view cfg-headers/gprs/l1sw.cfg @ 605:07d0dc4431f4

bootloader.s: same MEMIF fix as in int.s plus DPLL BYPASS fix Both MEMIF and DPLL settings are now the same between int.s and bootloader.s assembly code paths. Previously bootloader.s was setting DPLL BYPASS /2 mode, which persisted until _INT_Initialize code with the bootloader body omitted, or was changed to /1 in the hardware init function in the bootloader.lib:start.obj module.
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 17 Jun 2019 18:40:32 +0000
parents fd8227e3047d
children
line wrap: on
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#ifndef __L1SW_CFG__
#define __L1SW_CFG__
#define AMR 1
#define CUST 0
#define DCO_ALGO 0
#define IDS 1
#define L1_12NEIGH 1
#define L1_EOTD 0
#define L1_EOTD_QBIT_ACC 0
#define L1_GPRS 1
#define L1_GTT 0
#define L1_MIDI 0
#define L1_VOICE_MEMO_AMR 1
#define MELODY_E2 1
#define OP_L1_STANDALONE 0
#define OP_RIV_AUDIO 1
#define ORDER2_TX_TEMP_CAL 1
#define RAZ_VULSWITCH_REGAUDIO 0
#define SECURITY 0
#define SPEECH_RECO 1
#define TESTMODE 1
#define TRACE_TYPE 4
#define VCXO_ALGO 1
#endif /* __L1SW_CFG__ */