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comparison src/cs/system/main/init.c @ 603:b13731665274

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init.c MEMIF configuration revamped as described in the MEMIF-wait-states article in freecalypso-docs
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 17 Jun 2019 01:36:38 +0000
parents 92dbfa906f66
children 238b67a785f2
comparison
equal deleted inserted replaced
602:92dbfa906f66 603:b13731665274
498 */ 498 */
499 RHEA_INITRHEA(0,0,0xFF); 499 RHEA_INITRHEA(0,0,0xFF);
500 DPLL_INIT_BYPASS_MODE(DPLL_BYPASS_DIV_1); 500 DPLL_INIT_BYPASS_MODE(DPLL_BYPASS_DIV_1);
501 #if (CHIPSET == 8) 501 #if (CHIPSET == 8)
502 DPLL_INIT_DPLL_CLOCK(DPLL_LOCK_DIV_1, 6); 502 DPLL_INIT_DPLL_CLOCK(DPLL_LOCK_DIV_1, 6);
503 #elif (CHIPSET == 10) 503 #elif (CHIPSET == 10) || (CHIPSET == 11)
504 DPLL_INIT_DPLL_CLOCK(DPLL_LOCK_DIV_1, 8); 504 DPLL_INIT_DPLL_CLOCK(DPLL_LOCK_DIV_1, 8);
505 #else 505 #else
506 #error "We only have DPLL setup for CHIPSETs 8 and 10" 506 #error "We only have DPLL setup for CHIPSETs 8 and 10"
507 #endif 507 #endif
508 CLKM_InitARMClock(0x00, 2, 0); /* no low freq, no ext clock, div by 1 */ 508 CLKM_InitARMClock(0x00, 2, 0); /* no low freq, no ext clock, div by 1 */
509 /* 509 /*
510 * FreeCalypso change: memory timings and widths 510 * FreeCalypso change: memory timings and widths are target-dependent;
511 * are target-dependent. 511 * please refer to the MEMIF-wait-states document in the freecalypso-docs
512 * repository for the full explanation.
512 */ 513 */
513 #ifdef CONFIG_TARGET_PIRELLI 514 #ifdef CONFIG_TARGET_PIRELLI
514 /* 515 /*
515 * Pirelli's version of this Init_Target() function 516 * Pirelli's version of this Init_Target() function
516 * in their fw does the following: 517 * in their fw does the following:
518 MEM_INIT_CS0(4, MEM_DVS_16, MEM_WRITE_EN, 0); 519 MEM_INIT_CS0(4, MEM_DVS_16, MEM_WRITE_EN, 0);
519 MEM_INIT_CS1(4, MEM_DVS_16, MEM_WRITE_EN, 0); 520 MEM_INIT_CS1(4, MEM_DVS_16, MEM_WRITE_EN, 0);
520 MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0); 521 MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0);
521 MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0); 522 MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0);
522 MEM_INIT_CS4(7, MEM_DVS_16, MEM_WRITE_EN, 0); 523 MEM_INIT_CS4(7, MEM_DVS_16, MEM_WRITE_EN, 0);
523 #elif defined(CONFIG_TARGET_FCFAM) 524 #elif defined(CONFIG_TARGET_C155)
524 /* 525 /*
525 * The settings currently adopted for the FreeCalypso 526 * C155/156 official fw MEMIF config is almost the same as Pirelli's,
526 * hardware family, only nCS0, nCS1 and nCS2 are used 527 * only nCS4 WS is different, but nCS4 is unused on this model...
527 * presently.
528 */ 528 */
529 MEM_INIT_CS0(4, MEM_DVS_16, MEM_WRITE_EN, 0); 529 MEM_INIT_CS0(4, MEM_DVS_16, MEM_WRITE_EN, 0);
530 MEM_INIT_CS1(4, MEM_DVS_16, MEM_WRITE_EN, 0); 530 MEM_INIT_CS1(4, MEM_DVS_16, MEM_WRITE_EN, 0);
531 MEM_INIT_CS2(4, MEM_DVS_16, MEM_WRITE_EN, 0); 531 MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0);
532 MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0); 532 MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0);
533 MEM_INIT_CS4(4, MEM_DVS_16, MEM_WRITE_EN, 0); 533 MEM_INIT_CS4(6, MEM_DVS_16, MEM_WRITE_EN, 0);
534 #elif defined(CONFIG_TARGET_DSAMPLE) && (CHIPSET == 8) 534 #elif defined(CONFIG_TARGET_C11X) || defined(CONFIG_TARGET_C139) || \
535 /* 535 defined(CONFIG_TARGET_GTAMODEM)
536 * On D-Sample C05 (older Calypso silicon version) the clocks
537 * run slower: the ARM clock runs at 39 MHz instead of 52 MHz.
538 * Therefore, we need to use fewer wait states to effect
539 * the same memory speed.
540 */
541 MEM_INIT_CS0(2, MEM_DVS_16, MEM_WRITE_EN, 0);
542 MEM_INIT_CS1(2, MEM_DVS_16, MEM_WRITE_EN, 0);
543 MEM_INIT_CS2(2, MEM_DVS_16, MEM_WRITE_EN, 0);
544 MEM_INIT_CS3(2, MEM_DVS_16, MEM_WRITE_EN, 0);
545 MEM_INIT_CS4(0, MEM_DVS_8, MEM_WRITE_EN, 0);
546 #else
547 /* 536 /*
548 * The original settings from Openmoko, 537 * The original settings from Openmoko,
549 * only nCS0 and nCS1 are actually used, 538 * only nCS0 and nCS1 are actually used,
550 * same as on Mot C1xx phones, 539 * same as on Mot C1xx phones,
551 * the nCS2/3/4 settings are dummies from TI. 540 * the nCS2/3/4 settings are dummies from TI.
553 MEM_INIT_CS0(3, MEM_DVS_16, MEM_WRITE_EN, 0); 542 MEM_INIT_CS0(3, MEM_DVS_16, MEM_WRITE_EN, 0);
554 MEM_INIT_CS1(3, MEM_DVS_16, MEM_WRITE_EN, 0); 543 MEM_INIT_CS1(3, MEM_DVS_16, MEM_WRITE_EN, 0);
555 MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0); 544 MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0);
556 MEM_INIT_CS3(3, MEM_DVS_16, MEM_WRITE_EN, 0); 545 MEM_INIT_CS3(3, MEM_DVS_16, MEM_WRITE_EN, 0);
557 MEM_INIT_CS4(0, MEM_DVS_8, MEM_WRITE_EN, 0); 546 MEM_INIT_CS4(0, MEM_DVS_8, MEM_WRITE_EN, 0);
547 #elif defined(CONFIG_TARGET_J100)
548 /*
549 * Same as Mot C11x/12x/139/140 and Openmoko except for nCS2 WS:
550 * it appears that SE J100 has its ringtone melody generator chip
551 * hooked up there.
552 */
553 MEM_INIT_CS0(3, MEM_DVS_16, MEM_WRITE_EN, 0);
554 MEM_INIT_CS1(3, MEM_DVS_16, MEM_WRITE_EN, 0);
555 MEM_INIT_CS2(6, MEM_DVS_16, MEM_WRITE_EN, 0);
556 MEM_INIT_CS3(3, MEM_DVS_16, MEM_WRITE_EN, 0);
557 MEM_INIT_CS4(0, MEM_DVS_8, MEM_WRITE_EN, 0);
558 #elif (CHIPSET == 8)
559 /*
560 * Our only Calypso C05 target is Mother Mychaela's D-Sample board.
561 * WS=3 with the ARM7 core running at 39 MHz gives us 92 ns,
562 * so we should be good on this board.
563 */
564 MEM_INIT_CS0(3, MEM_DVS_16, MEM_WRITE_EN, 0);
565 MEM_INIT_CS1(3, MEM_DVS_16, MEM_WRITE_EN, 0);
566 MEM_INIT_CS2(3, MEM_DVS_16, MEM_WRITE_EN, 0);
567 MEM_INIT_CS3(3, MEM_DVS_16, MEM_WRITE_EN, 0);
568 MEM_INIT_CS4(0, MEM_DVS_8, MEM_WRITE_EN, 0);
569 #elif (CHIPSET == 10) || (CHIPSET == 11)
570 /*
571 * Default for Calypso C035 targets in the absence of a more specific
572 * selection above. We put the WS=4 memory-oriented setting on all
573 * chip selects so we automatically cover targets with a second flash
574 * chip select no matter if it's nCS2, nCS3 or nCS4, as well as even
575 * weirder targets with XRAM somewhere other than nCS1.
576 */
577 MEM_INIT_CS0(4, MEM_DVS_16, MEM_WRITE_EN, 0);
578 MEM_INIT_CS1(4, MEM_DVS_16, MEM_WRITE_EN, 0);
579 MEM_INIT_CS2(4, MEM_DVS_16, MEM_WRITE_EN, 0);
580 MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0);
581 MEM_INIT_CS4(4, MEM_DVS_16, MEM_WRITE_EN, 0);
582 #else
583 #error "Unknown MEMIF configuration"
558 #endif 584 #endif
559 MEM_INIT_CS6(0, MEM_DVS_32, MEM_WRITE_EN, 0); 585 MEM_INIT_CS6(0, MEM_DVS_32, MEM_WRITE_EN, 0);
560 MEM_INIT_CS7(0, MEM_DVS_32, MEM_WRITE_DIS, 0); 586 MEM_INIT_CS7(0, MEM_DVS_32, MEM_WRITE_DIS, 0);
561 RHEA_INITAPI(0,1); 587 RHEA_INITAPI(0,1);
562 RHEA_INITARM(0,0); 588 RHEA_INITARM(0,0);