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comparison src/cs/system/template/gsm_ds_motc155.template @ 536:ae18f9aad7ce

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C155 target support implemented in a way that should work with this model's original bootloader
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 05 Nov 2018 23:15:45 +0000
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535:bb9a08797022 536:ae18f9aad7ce
1 /*
2 * Integrated Protocol Stack Linker command file (all components)
3 *
4 * Target : ARM
5 *
6 * Copyright (c) Texas Instruments 2002, Condat 2002
7 *
8 * This version of the linker script template has been concocted
9 * by Spacefalcon the Outlaw based on previous hacks.
10 */
11
12 -c /* Autoinitialize variables at runtime */
13
14 /*********************************/
15 /* SPECIFY THE SYSTEM MEMORY MAP */
16 /*********************************/
17
18 MEMORY
19 {
20 /* CS0: Flash 4 Mbytes ****************************************************/
21 /* Interrupt Vectors Table */
22 I_MEM (RXI) : org = 0x00000000 len = 0x00000100
23
24 /* Boot Sector */
25 B_MEM (RXI) : org = 0x00000100 len = 0x00001f00
26
27 /* Magic Word for Calypso Boot ROM */
28 MWC_MEM (RXI) : org = 0x00002000 len = 0x00000004 fill = 0x0000001
29
30 /* Program Memory */
31 P_MEM1 (RXI) : org = 0x000200E0 len = 0x00000700
32 P_MEM2 (RXI) : org = 0x000207E0 len = 0x00000004
33 P_MEM3 (RXI) : org = 0x000207E4 len = 0x00400000
34
35 /* FFS Area */
36 FFS_MEM (RX) : org = 0x00700000 len = 0x000D0000
37 /**************************************************************************/
38
39 /* CS1: External SRAM 2 Mbytes ********************************************/
40 /* Data Memory */
41
42 /* We do the same splitting hack as on other targets */
43
44 D_MEM1 (RW) : org = 0x01000000 len = 0x00100000
45 D_MEM2 (RW) : org = 0x01100000 len = 0x00100000
46 /**************************************************************************/
47
48 /* CS6: Calypso Internal SRAM 256 kbytes **********************************/
49 /* Code & Variables Memory */
50 S_MEM (RXW) : org = 0x00800000 len = 0x00040000
51 /**************************************************************************/
52 }
53
54 /***********************************************/
55 /* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */
56 /***********************************************/
57
58 /*
59 * Since the bootloader directly calls the INT_Initialize() routine located
60 * in int.s, this int.s code must always be mapped at the same address
61 * (usually in the second flash sector). Its length is about 0x500 bytes.
62 * Then comes the code that need to be loaded into the internal RAM.
63 */
64
65 SECTIONS
66 {
67 .intvecs : {} > I_MEM /* Interrupt Vectors Table */
68 .monitor : > B_MEM /* Monitor Constants & Code */
69 {
70 $(CONST_BOOT_LIB)
71 }
72
73 .inttext : {} > P_MEM1 /* int.s Code */
74
75 .bss_dar : > D_MEM1 /* DAR SWE Variables */
76 {
77 $(BSS_DAR_LIB)
78 }
79
80 /*
81 * The .bss section should not be split to ensure it is initialized to 0
82 * each time the SW is reset. So the whole .bss is mapped either in D_MEM1
83 * or in D_MEM2.
84 *
85 * Falcon's note for K5A3281: see the comments above where the memory
86 * regions are defined.
87 */
88
89 .bss : > D_MEM1 | D_MEM2 /* Global & Static Variables */
90 {
91 $(BSS_BOOT_LIB)
92 }
93
94 /*
95 * All .bss sections, which must be mapped in internal RAM must be
96 * grouped in order to initialized the corresponding memory to 0.
97 * This initialization is done in int.s file before calling the Nucleus
98 * routine.
99 */
100
101 GROUP
102 {
103 S_D_Mem /* Label of start address of .bss section in Int. RAM */
104 .DintMem
105 {
106
107 /*
108 * .bss sections of the application
109 */
110
111 $(BSS_LIBS)
112
113 }
114
115 API_HISR_stack : {}
116
117 E_D_Mem /* Label of end address of .bss section in Int. RAM */
118 } > S_MEM
119
120 /*
121 * .text and .const sections which must be mapped in internal RAM.
122 */
123
124 .ldfl : {} > P_MEM2 /* Used to know the start load address */
125 GROUP load = P_MEM3, run = S_MEM
126 {
127 S_P_Mem /* Label of start address of .text & .const sections in Int. RAM */
128 .PIntMem
129 {
130 /*
131 * .text and .const sections of the application.
132 *
133 * The .veneer sections correspond exactly to .text:v&n sections
134 * implementing the veneer functions. The .text:v$n -> .veneer
135 * translation is performed by PTOOL software when PTOOL_OPTIONS
136 * environement variable is set to veneer_section.
137 */
138
139 $(CONST_LIBS)
140
141 }
142 E_P_Mem /* Label of end address of .text and .const sections in Int. RAM */
143 }
144
145 /*
146 * The rest of the code is mapped in flash, however the trampolines
147 * load address should be consistent with .text.
148 */
149 COMMENT2START
150 `trampolines load = P_MEM3, run = S_MEM
151 COMMENT2END
152
153 .text : {} > P_MEM3 /* Code */
154
155 /*
156 * The rest of the constants is mapped in flash.
157 * The .cinit section should not be split.
158 */
159
160 .cinit : {} > P_MEM3 /* Initialization Tables */
161 .const : {} > P_MEM3 /* Constant Data */
162 KadaAPI : {} > P_MEM3 /* ROMized CLDC */
163
164 .javastack: {} >> D_MEM1 | D_MEM2 /* Java stack */
165
166 .stackandheap : > D_MEM1 /* System Stacks, etc... */
167 {
168 /* Leave 20 32bit words for register pushes. */
169 . = align(8);
170 . += 20 * 4;
171
172 /* Stack for abort and/or undefined modes. */
173 exception_stack = .;
174
175 /* Leave 38 32bit words for state saving on exceptions. */
176 _xdump_buffer = .;
177 . += 38 * 4;
178 . = align(8);
179
180 /* Beginning of stacks and heap area - 2.75 kbytes (int.s) */
181 stack_segment = .;
182 . += 0xB00;
183 }
184
185 .data : {} > D_MEM1 /* Initialized Data */
186 .sysmem : {} > D_MEM1 /* Dynamic Memory Allocation Area */
187
188 }