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comparison src/cs/system/Main/init.c @ 269:a498108254c9

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init.c: Init_Target() reconstructed, perfect match to original object
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 06 Aug 2017 17:08:19 +0000
parents f5c10ec9c5fd
children d5a34ea92f2a
comparison
equal deleted inserted replaced
268:f5c10ec9c5fd 269:a498108254c9
488 #if (RF_FAM == 43) && (BOARD == 46) 488 #if (RF_FAM == 43) && (BOARD == 46)
489 CLKM_USE_VTCXO_26MHZ; 489 CLKM_USE_VTCXO_26MHZ;
490 #endif 490 #endif
491 #endif 491 #endif
492 492
493 #if (CHIPSET ==15) 493
494 //Enable APLL
495 *((volatile unsigned short *) (C_MAP_CLKM_BASE+0x10)) = 0x01|0x6;
496 // UART Clock from APLL
497 *((volatile unsigned short *) CLKM_CNTL_CLK_PROG_FREE_RUNN) = 0x0001;
498 (*(volatile Uint16 *) 0xFFFF702A) = 0x0002;//reset the UART module.
499
500 #endif
501
502
503
504
505 //
506 // Control HOM/SAM automatic switching 494 // Control HOM/SAM automatic switching
507 //-------------------------------------------------- 495 //--------------------------------------------------
508 *((volatile unsigned short *) CLKM_CNTL_CLK) &= ~CLKM_EN_IDLE3_FLG; 496 *((volatile unsigned short *) CLKM_CNTL_CLK) &= ~CLKM_EN_IDLE3_FLG;
497
498 /*
499 * The following part has been reconstructed from disassembly.
500 */
501 RHEA_INITRHEA(0,0,0xFF);
502 DPLL_INIT_BYPASS_MODE(DPLL_BYPASS_DIV_1);
503 DPLL_INIT_DPLL_CLOCK(DPLL_LOCK_DIV_1, 8);
504 CLKM_InitARMClock(0x00, 2, 0); /* no low freq, no ext clock, div by 1 */
505 MEM_INIT_CS0(3, MEM_DVS_16, MEM_WRITE_EN, 0);
506 MEM_INIT_CS1(3, MEM_DVS_16, MEM_WRITE_EN, 0);
507 MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0);
508 MEM_INIT_CS3(3, MEM_DVS_16, MEM_WRITE_EN, 0);
509 MEM_INIT_CS4(0, MEM_DVS_8, MEM_WRITE_EN, 0);
510 MEM_INIT_CS6(0, MEM_DVS_32, MEM_WRITE_EN, 0);
511 MEM_INIT_CS7(0, MEM_DVS_32, MEM_WRITE_DIS, 0);
512 RHEA_INITAPI(0,1);
513 RHEA_INITARM(0,0);
514 DPLL_SET_PLL_ENABLE;
509 515
510 /* 516 /*
511 * Disable and Clear all pending interrupts 517 * Disable and Clear all pending interrupts
512 */ 518 */
513 #if (CHIPSET == 12) || (CHIPSET == 15) 519 #if (CHIPSET == 12) || (CHIPSET == 15)
516 F_INTH_VALID_NEXT(C_INTH_IRQ); // reset current IT in INTH IRQ 522 F_INTH_VALID_NEXT(C_INTH_IRQ); // reset current IT in INTH IRQ
517 F_INTH_VALID_NEXT(C_INTH_FIQ); // reset current IT in INTH FIQ 523 F_INTH_VALID_NEXT(C_INTH_FIQ); // reset current IT in INTH FIQ
518 F_INTH_RESET_ALL_IT; // reset all IRQ/FIQ source 524 F_INTH_RESET_ALL_IT; // reset all IRQ/FIQ source
519 #else 525 #else
520 INTH_DISABLEALLIT; 526 INTH_DISABLEALLIT;
521 INTH_RESETALLIT; 527 #if 0 /* not present in our reference binary object */
528 INTH_RESETALLIT;
529 #endif
522 INTH_CLEAR; /* reset IRQ/FIQ source */ 530 INTH_CLEAR; /* reset IRQ/FIQ source */
523 #endif
524
525 #if (CHIPSET == 12)
526 /* API-RHEA control register configuration */
527 f_memif_init_api_rhea_ctrl(C_MEMIF_API_RHEA_ADAPT,
528 C_MEMIF_API_RHEA_ADAPT,
529 C_MEMIF_API_RHEA_ADAPT,
530 C_MEMIF_API_RHEA_NO_DEBUG);
531
532 #if ((BOARD == 43) || (BOARD == 45))
533 // if Esample,Evaconso active extended page mode
534 // With Calypso+ chipset, extended page mode can be enabled
535 // only if W_A_CALYPSO_PLUS_SPR_19599 is set to one in l1_confg.h.
536 // see L1_MCU-SPR-17515 and L1_MCU-SPR-19599 for more information
537 f_memif_extended_page_mode_enable();
538 #endif
539 #endif /* (CHIPSET == 12) */
540
541 #if (CHIPSET == 15)
542 /* API-RHEA control register configuration */
543 f_emif_api_rhea_conf(C_RHEA_STROBE0_ACCESS_SIZE_ADAPT_ENABLE,
544 C_RHEA_STROBE1_ACCESS_SIZE_ADAPT_ENABLE,
545 C_API_ACCESS_SIZE_ADAPT_ENABLE,
546 C_ARM_DEBUG_DISABLE);
547 #if (BOARD == 70) || (BOARD == 71)
548 // set the EMIF settings here for locosto
549 // We could have the default settings here and
550 // then change it after dynamic clock config
551 /* MCP RAM Setting Is being done here */
552 #if 0 /* This is commented out by Ranga */
553 #if (PSP_FAILSAFE!=1)
554 bcrTmpVal = *((volatile unsigned char *)0x007FFFFFE);
555 bcrTmpVal +=1;
556 bcrTmpVal = *((volatile unsigned char *)0x007FFFFFE);
557 *((volatile unsigned char *)0x007FFFFFE)=0x0001;
558 *((volatile unsigned char *)0x007FFFFFE)=0x1542;
559
560 /* Setting NOR Flash to these 3 Wait State */
561 *((volatile char *)0x06000AAA)=0xAA;
562 *((volatile char *)0x06000555)=0x55;
563 *((volatile char *)0x06016AAA)=0xC0;
564 #endif
565 #endif
566 #endif
567 #endif /* (CHIPSET == 15) */
568
569
570 // Write_en_0 = 0 , Write_en_1 = 0
571 RHEA_INITARM(0,0);
572
573 #if (CHIPSET ==15)
574 // Mark USB on 52 MHZ Clock
575 *((volatile unsigned short *) (CLKM_CNTL_CLK_USB)) = 0x02;
576 #endif
577
578 #if (CHIPSET == 12) || ((CHIPSET == 10) && (OP_WCP == 1))
579 /* Allocate the 0.5 Mbits Shared RAM to the DSP */
580 f_memif_shared_sram_allocation(C_MEMIF_DSPMS_0_5MBITS_TO_DSP);
581 #endif 531 #endif
582 532
583 // INTH 533 // INTH
584 //-------------------------------------------------- 534 //--------------------------------------------------
585 #if (CHIPSET == 12) || (CHIPSET == 15) 535 #if (CHIPSET == 12) || (CHIPSET == 15)
689 *((volatile SYS_UWORD16 *)ULDP_SETUP_FRAME_REG) = SETUP_FRAME; // 3 frames 639 *((volatile SYS_UWORD16 *)ULDP_SETUP_FRAME_REG) = SETUP_FRAME; // 3 frames
690 *((volatile SYS_UWORD16 *)ULDP_SETUP_VTCXO_REG) = SETUP_VTCXO; // 0 periods 640 *((volatile SYS_UWORD16 *)ULDP_SETUP_VTCXO_REG) = SETUP_VTCXO; // 0 periods
691 *((volatile SYS_UWORD16 *)ULDP_SETUP_SLICER_REG) = SETUP_SLICER; // 31 periods 641 *((volatile SYS_UWORD16 *)ULDP_SETUP_SLICER_REG) = SETUP_SLICER; // 31 periods
692 *((volatile SYS_UWORD16 *)ULDP_SETUP_CLK13_REG) = SETUP_CLK13; // 31 periods 642 *((volatile SYS_UWORD16 *)ULDP_SETUP_CLK13_REG) = SETUP_CLK13; // 31 periods
693 *((volatile SYS_UWORD16 *)ULPD_SETUP_RF_REG) = SETUP_RF; // 31 periods 643 *((volatile SYS_UWORD16 *)ULPD_SETUP_RF_REG) = SETUP_RF; // 31 periods
694 #endif
695
696 #if (CHIPSET == 15)
697 *((volatile SYS_UWORD16 *)ULPD_DCXO_SETUP_SLEEPN) = SETUP_SLEEPZ; // 0
698 *((volatile SYS_UWORD16 *)ULPD_DCXO_SETUP_SYSCLKEN) = SETUP_SYSCLKEN; // 255 clocks of 32 KHz for 7.8 ms DCXO delay for Locosto
699 *((volatile SYS_UWORD16 *)0xFFFEF192) = 0x1; //CLRZ
700 *((volatile SYS_UWORD16 *)0xFFFEF190) = 0x2; //SLPZ
701 *((volatile SYS_UWORD16 *)0xFFFEF18E)= 0x2; //SYSCLKEN
702 *((volatile SYS_UWORD16 *)0xFFFEF186) = 0x2; //CLK13_EN
703 *((volatile SYS_UWORD16 *)0xFFFEF18A) = 0x2; //DRP_DBB_SYSCLK
704
705
706
707
708 #endif 644 #endif
709 645
710 // Set Gauging versus HF (PLL) 646 // Set Gauging versus HF (PLL)
711 //================================================= 647 //=================================================
712 ULDP_GAUGING_SET_HF; // Enable gauging versus HF 648 ULDP_GAUGING_SET_HF; // Enable gauging versus HF
774 *((volatile SYS_UWORD16 *) 0xFFFFFD04) &= ~(0x4); 710 *((volatile SYS_UWORD16 *) 0xFFFFFD04) &= ~(0x4);
775 #endif 711 #endif
776 712
777 // set the debug latch to 0x0000. 713 // set the debug latch to 0x0000.
778 *((volatile SYS_UWORD16 *) 0x2700000) = 0x0000; 714 *((volatile SYS_UWORD16 *) 0x2700000) = 0x0000;
779 #elif ((BOARD == 70) || (BOARD == 71))
780 AI_InitIOConfig();
781 /* Mark The System configuration According to I-Sample */
782 /* Adding GPIO Mux Setting Here */
783 pin_configuration_all(); // Init Tuned for Power Management
784 /* A22 is Enabled in int.s hence not Here */
785 /* FIXME: PULL_UP Enable and PULL UP Values Need to revisited */
786
787 /* Add code to find out the manufacture id of NOR flash*/
788
789 // Copy ffsdrv_device_id_read() function code to RAM. The only known
790 // way to determine the size of the code is to look either in the
791 // linker-generated map file or in the assember output file.
792 ffsdrv_copy_code_to_ram((UWORD16 *) detect_code,
793 (UWORD16 *) &ffsdrv_device_id_read,
794 sizeof(detect_code));
795
796 // Combine bit 0 of the thumb mode function pointer with the address
797 // of the code in RAM. Then call the detect function in RAM.
798 myfp = (pf_t) (((int) &ffsdrv_device_id_read & 1) | (int) detect_code);
799 (*myfp)(0x06000000, &manufact, device_id);
800
801 enable_ps_ram_burst();
802
803 if( 0x7e == device_id[0] )
804 {
805 enable_flash_burst();
806 flash_device_id = 0x7E;
807 }
808 else
809 {
810 enable_flash_burst_mirror();
811 flash_device_id = 0;
812 }
813
814
815 asm(" NOP");
816 asm(" NOP");
817 asm(" NOP");
818 asm(" NOP");
819 asm(" NOP");
820 asm(" NOP");
821 asm(" NOP");
822 asm(" NOP");
823
824 #if 0 // Init Changed for tuning to Power Management -Old Init Commented
825 /* Ball N9 Mapped to TSPACT_8 (TPU) */
826 F_IO_CONFIG(C_CONF_GPIO_5,C_CONF_PUPD_EN|0x01);
827 /* Ball A6 ND_WE */
828 F_IO_CONFIG(C_CONF_GPIO_18,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01);
829 /* Ball C2 ND_RDY */
830 F_IO_CONFIG(C_CONF_GPIO_34,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01);
831 /* Ball C3 ND_RE */
832 F_IO_CONFIG(C_CONF_GPIO_31,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01);
833 /* BALL E5 CAM_D_4 */
834 F_IO_CONFIG(C_CONF_ND_NWP,0x02);
835 /* BALL F6 ND_CLE */
836 F_IO_CONFIG(C_CONF_GPIO_32,C_CONF_PUPD_EN|0x01);
837 /* BALL H8 ND_ALE */
838 F_IO_CONFIG(C_CONF_GPIO_33,C_CONF_PUPD_EN|0x01);
839 /* BALL E10 LCD_NCS0 */
840 F_IO_CONFIG(C_CONF_GPIO_13,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01);
841 /* BALL C11 GPIO_10 */
842 F_IO_CONFIG(C_CONF_GPIO_10,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01);
843 /* BALL D10 GPIO_11 */
844 F_IO_CONFIG(C_CONF_GPIO_11,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01);
845 /* BALL M6 CAM_D_1 */
846 F_IO_CONFIG(C_CONF_GPIO_0,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x02);
847 /* BALL N5 CAM_D_0 */
848 F_IO_CONFIG(C_CONF_GPIO_47,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x02);
849 /* BALL A5 CAM_LCLK */
850 F_IO_CONFIG(C_CONF_GPIO_21,0x01);
851 /* BALL C6 CAM_XCLK */
852 F_IO_CONFIG(C_CONF_GPIO_22,0x01);
853 /* BALL E7 CAM_VS */
854 F_IO_CONFIG(C_CONF_GPIO_20,0x01);
855 /* BALL F8 CAM_HS */
856 F_IO_CONFIG(C_CONF_GPIO_19,0x01);
857 /* BALL K7 MCSI_TX */
858 F_IO_CONFIG(C_CONF_GPIO_45,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01);
859 /* BALL M5 MCSI_FS */
860 F_IO_CONFIG(C_CONF_GPIO_44,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01);
861 /* BALL N3 MCSI_CK */
862 F_IO_CONFIG(C_CONF_GPIO_43,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01);
863 /* BALL P2 MCSI_RX */
864 F_IO_CONFIG(C_CONF_GPIO_46,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01);
865 /* BALL B11 TSPACT_10 */
866 F_IO_CONFIG(C_CONF_GPIO_12,C_CONF_PUPD_EN|0x01);
867 /* BALL B3 CAM_D_5 */
868 F_IO_CONFIG(C_CONF_GPIO_30,C_CONF_PUPD_EN|0x03);
869 /* BALL C4 CAM_D_7 */
870 F_IO_CONFIG(C_CONF_GPIO_28,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x03);
871 /* BALL C5 SPI_DATA_MOSI */
872 F_IO_CONFIG(C_CONF_GPIO_25,C_CONF_PUPD_EN|0x01);
873 /* BALL E6 SPI_NCS0 */
874 F_IO_CONFIG(C_CONF_GPIO_26,C_CONF_PUPD_EN|0x01);
875 /* BALL F7 SPI_DATA_MIS0 */
876 F_IO_CONFIG(C_CONF_GPIO_24,C_CONF_PUPD_EN|0x03);
877 /* BALL G6 CAM_D_2 */
878 F_IO_CONFIG(C_CONF_GPIO_7,C_CONF_PUPD_EN|0x05);
879 /* BALL G7 CAM_D_6 */
880 F_IO_CONFIG(C_CONF_GPIO_29,C_CONF_PUPD_EN|0x03);
881 /* BALL G8 SPI_NCS1 */
882 F_IO_CONFIG(C_CONF_GPIO_27,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01);
883 /* BALL G9 SPI_CLK */
884 F_IO_CONFIG(C_CONF_GPIO_23,C_CONF_PUPD_EN|0x01);
885 /* BALL L6 CKM */
886 F_IO_CONFIG(C_CONF_GPIO_42,C_CONF_PUPD_VAL|C_CONF_PUPD_EN|0x01);
887
888 /*By default the muxed bus is given to LCD*/
889 C_CONF_LCD_CAM_NAN_REG=0x03;
890
891 #endif // for #if 0 Init Changed for Power Management
892 #endif // BOARD 715 #endif // BOARD
893 716
894 // Enable HW Timers 1 & 2 717 // Enable HW Timers 1 & 2
895 TM_EnableTimer (1); 718 TM_EnableTimer (1);
896 TM_EnableTimer (2); 719 TM_EnableTimer (2);
897 720
898 asm(" NOP");
899 asm(" NOP");
900 asm(" NOP");
901 asm(" NOP");
902 asm(" NOP");
903 asm(" NOP");
904 asm(" NOP");
905 asm(" NOP");
906 asm(" NOP");
907 asm(" NOP");
908 asm(" NOP");
909 asm(" NOP");
910 asm(" NOP");
911 asm(" NOP");
912 asm(" NOP");
913 asm(" NOP");
914 asm(" NOP");
915 asm(" NOP");
916 asm(" NOP");
917 asm(" NOP");
918 asm(" NOP");
919 asm(" NOP");
920 asm(" NOP");
921 asm(" NOP");
922 #endif /* (OP_L1_STANDALONE == 0) */ 721 #endif /* (OP_L1_STANDALONE == 0) */
923 722
924 #endif /* #if (BOARD == 5) */ 723 #endif /* #if (BOARD == 5) */
925 #if(OP_L1_STANDALONE == 1 && MIRROR_BIT == 1 ) //temp FIX for L1 standalone-this fix will work only for I-sample mirror bit
926 //#if(OP_L1_STANDALONE == 1 )
927 //AI_InitIOConfig();
928 //pin_configuration_all(); // Init Tuned for Power Management
929 //enable_ps_ram_burst();
930 //enable_flash_burst_mirror();
931 flash_device_id = 0;
932 //asm(" NOP");
933 //asm(" NOP");
934 //asm(" NOP");
935 //asm(" NOP");
936 //asm(" NOP");
937 //asm(" NOP");
938 //asm(" NOP");
939 //asm(" NOP");
940 #elif(OP_L1_STANDALONE == 1 && MIRROR_BIT == 0 )
941 flash_device_id = 0x7E;
942 #endif
943
944
945 #if GSM_IDLE_RAM_DEBUG
946 #if (CHIPSET!=15)
947 *((volatile SYS_UWORD16 *) 0xFFFE4806) = (0x0020);
948 AI_ConfigBitAsOutput(3);
949 AI_ConfigBitAsOutput(2);
950 #endif
951 #endif
952 #if (CHIPSET==15)
953 {
954 volatile unsigned int * configReg=(volatile unsigned int *)0xFFFEF01C;
955 *configReg &= 0xF7FF;
956 }
957 #endif
958
959 } 724 }
960 725
961 /* 726 /*
962 * Init_Drivers 727 * Init_Drivers
963 * 728 *