FreeCalypso > hg > fc-magnetite

comparison src/cs/system/template/gsm_ds_k5a3281.template @ 0:945cf7f506b2

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
src/cs: chipsetsw import from tcs211-fcmodem binary blobs and LCD demo files have been excluded, all line endings are LF only
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 25 Sep 2016 22:50:11 +0000
parents
children
comparison
equal deleted inserted replaced
-1:000000000000 0:945cf7f506b2
1 /*
2 * Integrated Protocol Stack Linker command file (all components)
3 *
4 * Target : ARM
5 *
6 * Copyright (c) Texas Instruments 2002, Condat 2002
7 *
8 * This version of the linker script template has been concocted
9 * by Spacefalcon the Outlaw, based on gsm_ds_amd8_lj3.template,
10 * in order to build the GSM firmware for the memory configuration
11 * found in the Openmoko GTA0x GSM modem, which consists of the
12 * K5A3281 flash+RAM MCP plus the 512 KiB of internal RAM in the
13 * Calypso (PD751992A) chip itself.
14 */
15
16 -c /* Autoinitialize variables at runtime */
17
18 /*********************************/
19 /* SPECIFY THE SYSTEM MEMORY MAP */
20 /*********************************/
21
22 MEMORY
23 {
24 /* CS0: Flash 4 Mbytes ****************************************************/
25 /* Interrupt Vectors Table */
26 I_MEM (RXI) : org = 0x00000000 len = 0x00000100
27
28 /* Boot Sector */
29 B_MEM (RXI) : org = 0x00000100 len = 0x00001f00
30
31 /* Magic Word for Calypso Boot ROM */
32 MWC_MEM (RXI) : org = 0x00002000 len = 0x00000004 fill = 0x0000001
33
34 /* Program Memory */
35 P_MEM1 (RXI) : org = 0x00004000 len = 0x00000700
36 P_MEM2 (RXI) : org = 0x00004700 len = 0x00000004
37 P_MEM3 (RXI) : org = 0x00004704 len = 0x002fb8fc
38
39 /* FFS Area */
40 FFS_MEM (RX) : org = 0x00380000 len = 0x00080000
41 /**************************************************************************/
42
43 /* CS1: External SRAM 1 Mbytes ********************************************/
44 /* Data Memory */
45
46 /*
47 *** HACK by Spacefalcon the Outlaw ***
48 *
49 * The starting Leonardo version (gsm_ds_amd8_lj3.template) had two
50 * external SRAM regions: D_MEM1 and D_MEM2. When I tried removing
51 * D_MEM2 and keeping only D_MEM1, the linker started behaving oddly
52 * in that the sections were emitted in the wrong order, and the
53 * addresses printed in the map file were bogus. The resulting m0
54 * images seemed to still work correctly, but I feel that having the
55 * linker act "correctly" is better.
56 *
57 * My current hack-solution is to split the 1 MiB physical XRAM
58 * into D_MEM1 and D_MEM2 of 512 KiB each. As it happens, the total
59 * XRAM usage of the current firmware is a little below 512 KiB anyway.
60 */
61
62 D_MEM1 (RW) : org = 0x01000000 len = 0x00080000
63 D_MEM2 (RW) : org = 0x01080000 len = 0x00080000
64 /**************************************************************************/
65
66 /* CS6: Calypso Internal SRAM 512 kbytes **********************************/
67 /* Code & Variables Memory */
68 S_MEM (RXW) : org = 0x00800000 len = 0x00080000
69 /**************************************************************************/
70 }
71
72 /***********************************************/
73 /* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */
74 /***********************************************/
75
76 /*
77 * Since the bootloader directly calls the INT_Initialize() routine located
78 * in int.s, this int.s code must always be mapped at the same address
79 * (usually in the second flash sector). Its length is about 0x500 bytes.
80 * Then comes the code that need to be loaded into the internal RAM.
81 */
82
83 SECTIONS
84 {
85 .intvecs : {} > I_MEM /* Interrupt Vectors Table */
86 .monitor : > B_MEM /* Monitor Constants & Code */
87 {
88 $(CONST_BOOT_LIB)
89 }
90
91 .inttext : {} > P_MEM1 /* int.s Code */
92
93 .bss_dar : > D_MEM1 /* DAR SWE Variables */
94 {
95 $(BSS_DAR_LIB)
96 }
97
98 /*
99 * The .bss section should not be split to ensure it is initialized to 0
100 * each time the SW is reset. So the whole .bss is mapped either in D_MEM1
101 * or in D_MEM2.
102 *
103 * Falcon's note for K5A3281: see the comments above where the memory
104 * regions are defined.
105 */
106
107 .bss : > D_MEM1 | D_MEM2 /* Global & Static Variables */
108 {
109 $(BSS_BOOT_LIB)
110 }
111
112 /*
113 * All .bss sections, which must be mapped in internal RAM must be
114 * grouped in order to initialized the corresponding memory to 0.
115 * This initialization is done in int.s file before calling the Nucleus
116 * routine.
117 */
118
119 GROUP
120 {
121 S_D_Mem /* Label of start address of .bss section in Int. RAM */
122 .DintMem
123 {
124
125 /*
126 * .bss sections of the application
127 */
128
129 $(BSS_LIBS)
130
131 }
132
133 API_HISR_stack : {}
134
135 E_D_Mem /* Label of end address of .bss section in Int. RAM */
136 } > S_MEM
137
138 /*
139 * .text and .const sections which must be mapped in internal RAM.
140 */
141
142 .ldfl : {} > P_MEM2 /* Used to know the start load address */
143 GROUP load = P_MEM3, run = S_MEM
144 {
145 S_P_Mem /* Label of start address of .text & .const sections in Int. RAM */
146 .PIntMem
147 {
148 /*
149 * .text and .const sections of the application.
150 *
151 * The .veneer sections correspond exactly to .text:v&n sections
152 * implementing the veneer functions. The .text:v$n -> .veneer
153 * translation is performed by PTOOL software when PTOOL_OPTIONS
154 * environement variable is set to veneer_section.
155 */
156
157 $(CONST_LIBS)
158
159 }
160 E_P_Mem /* Label of end address of .text and .const sections in Int. RAM */
161 }
162
163 /*
164 * The rest of the code is mapped in flash, however the trampolines
165 * load address should be consistent with .text.
166 */
167 COMMENT2START
168 `trampolines load = P_MEM3, run = S_MEM
169 COMMENT2END
170
171 .text : {} > P_MEM3 /* Code */
172
173 /*
174 * The rest of the constants is mapped in flash.
175 * The .cinit section should not be split.
176 */
177
178 .cinit : {} > P_MEM3 /* Initialization Tables */
179 .const : {} > P_MEM3 /* Constant Data */
180 KadaAPI : {} > P_MEM3 /* ROMized CLDC */
181
182 .javastack: {} >> D_MEM1 | D_MEM2 /* Java stack */
183
184 .stackandheap : > D_MEM1 /* System Stacks, etc... */
185 {
186 /* Leave 20 32bit words for register pushes. */
187 . = align(8);
188 . += 20 * 4;
189
190 /* Stack for abort and/or undefined modes. */
191 exception_stack = .;
192
193 /* Leave 38 32bit words for state saving on exceptions. */
194 _xdump_buffer = .;
195 . += 38 * 4;
196 . = align(8);
197
198 /* Beginning of stacks and heap area - 2.75 kbytes (int.s) */
199 stack_segment = .;
200 . += 0xB00;
201 }
202
203 .data : {} > D_MEM1 /* Initialized Data */
204 .sysmem : {} > D_MEM1 /* Dynamic Memory Allocation Area */
205
206 }