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comparison src/cs/drivers/drv_core/dma/dma.h @ 0:945cf7f506b2

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src/cs: chipsetsw import from tcs211-fcmodem binary blobs and LCD demo files have been excluded, all line endings are LF only
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 25 Sep 2016 22:50:11 +0000
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1 /******************************************************************************
2 TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
3
4 Property of Texas Instruments -- For Unrestricted Internal Use Only
5 Unauthorized reproduction and/or distribution is strictly prohibited. This
6 product is protected under copyright law and trade secret law as an
7 unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All
8 rights reserved.
9
10
11 Filename : dma.h
12
13 Description : DMA
14
15 Project : drivers
16
17 Author : pmonteil@tif.ti.com Patrice Monteil.
18
19 Version number : 1.12
20
21 Date : 05/23/03
22
23 Previous delta : 12/08/00 11:22:15
24
25 SCCS file : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/RELEASE_GPRS/drivers1/common/SCCS/s.dma.h
26
27 Sccs Id (SID) : '@(#) dma.h 1.6 01/30/01 10:22:23 '
28
29
30 *****************************************************************************/
31
32 #include "chipset.cfg"
33
34 /**** DMA configuration register ****/
35
36 #if (CHIPSET != 12)
37
38 // CONTROLLER_CONFIG register
39 //---------------------------
40 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
41 #define DMA_CONFIG_ADDR MEM_DMA_ADDR
42 #else
43 #define DMA_CONFIG_ADDR (MEM_DMA_ADDR + 0x20)
44 #endif
45 #define DMA_CONFIG_BURST 0x1c /* length of burst */
46
47 // ALLOC_CONFIG register
48 //---------------------------
49 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
50 #define DMA_ALLOC_CONFIG_ADDR (MEM_DMA_ADDR + 0x02)
51 #endif
52 #define DMA_CONFIG_ALLOC1 0x01 /* allocation for channel 1 */
53 #define DMA_CONFIG_ALLOC2 0x02 /* allocation for channel 2 */
54
55 // DMA Channel 1 configuration
56 //---------------------------
57
58 // DMA1_RAD register
59 //---------------------------
60 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
61 #define DMA1_RAD_ADDR (MEM_DMA_ADDR + 0x10)
62 #else
63 #define DMA1_RAD_ADDR MEM_DMA_ADDR
64 #endif
65 #define DMA_RHEA_ADDR 0x07ff /* rhea start address */
66 #define DMA_RHEA_CS 0xf800 /* rhea chip select */
67
68 // DMA1_RDPTH register
69 //---------------------------
70 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
71 #define DMA1_RDPTH_ADDR (MEM_DMA_ADDR + 0x12)
72 #else
73 #define DMA1_RDPTH_ADDR (MEM_DMA_ADDR + 0x02)
74 #endif
75 #define DMA_RHEA_LENGTH 0x07ff /* rhea buffer length */
76
77 // DMA1_AAD register
78 //---------------------------
79 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
80 #define DMA1_AAD_ADDR (MEM_DMA_ADDR + 0x14)
81 #else
82 #define DMA1_AAD_ADDR (MEM_DMA_ADDR + 0x04)
83 #endif
84 #define DMA_API_ADDR 0x0fff /* API start address */
85
86 // DMA1_ALGTH register
87 //---------------------------
88 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
89 #define DMA1_ALGTH_ADDR (MEM_DMA_ADDR + 0x16)
90 #else
91 #define DMA1_ALGTH_ADDR (MEM_DMA_ADDR + 0x06)
92 #endif
93 #define DMA_API_LENGTH 0x0fff /* API page length */
94
95 // DMA1_CTRL register
96 //---------------------------
97 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
98 #define DMA1_CTRL_ADDR (MEM_DMA_ADDR + 0x18)
99 #else
100 #define DMA1_CTRL_ADDR (MEM_DMA_ADDR + 0x08)
101 #endif
102 #define DMA_CTRL_ENABLE 0x0001 /* DMA enable */
103 #define DMA_CTRL_IDLE 0x0002 /* idle */
104 #define DMA_CTRL_ONE_SHOT 0x0004
105 #define DMA_CTRL_FIFO_MODE 0x0008
106 #define DMA_CTRL_CUR_PAGE 0x0010 /* current page # */
107 #define DMA_CTRL_MAS 0x0020
108 #define DMA_CTRL_START 0x0040 /* DMA start */
109 #define DMA_CTRL_IRQ_MODE 0x0080
110 #define DMA_CTRL_IRQ_STATE 0x0100
111 #define DMA_CTRL_RHEA_ABORT 0x0200
112 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
113 #define DMA_CTRL_PRIORITY 0x1800 /* Number of additional reading on the bus */
114 #endif
115
116 // DMA1_CUR_OFFSET_API register
117 //---------------------------
118 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
119 #define DMA1_OFFSET_ADDR (MEM_DMA_ADDR + 0x1A)
120 #else
121 #define DMA1_OFFSET_ADDR (MEM_DMA_ADDR + 0x0A)
122 #endif
123
124
125 // DMA Channel 2 configuration
126 //---------------------------
127
128 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
129 #define DMA2_RAD_ADDR (MEM_DMA_ADDR + 0x20)
130 #define DMA2_RDPTH_ADDR (MEM_DMA_ADDR + 0x22)
131 #define DMA2_AAD_ADDR (MEM_DMA_ADDR + 0x24)
132 #define DMA2_ALGTH_ADDR (MEM_DMA_ADDR + 0x26)
133 #define DMA2_CTRL_ADDR (MEM_DMA_ADDR + 0x28)
134 #define DMA2_OFFSET_ADDR (MEM_DMA_ADDR + 0x2A)
135 #else
136 #define DMA2_RAD_ADDR (MEM_DMA_ADDR + 0x10)
137 #define DMA2_RDPTH_ADDR (MEM_DMA_ADDR + 0x12)
138 #define DMA2_AAD_ADDR (MEM_DMA_ADDR + 0x14)
139 #define DMA2_ALGTH_ADDR (MEM_DMA_ADDR + 0x16)
140 #define DMA2_CTRL_ADDR (MEM_DMA_ADDR + 0x18)
141 #define DMA2_OFFSET_ADDR (MEM_DMA_ADDR + 0x1A)
142 #endif
143
144 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
145 // DMA Channel 3 configuration
146 //---------------------------
147
148 #define DMA3_RAD_ADDR (MEM_DMA_ADDR + 0x30)
149 #define DMA3_RDPTH_ADDR (MEM_DMA_ADDR + 0x32)
150 #define DMA3_AAD_ADDR (MEM_DMA_ADDR + 0x34)
151 #define DMA3_ALGTH_ADDR (MEM_DMA_ADDR + 0x36)
152 #define DMA3_CTRL_ADDR (MEM_DMA_ADDR + 0x38)
153 #define DMA3_OFFSET_ADDR (MEM_DMA_ADDR + 0x3A)
154
155 // DMA Channel 4 configuration
156 //---------------------------
157
158 #define DMA4_RAD_ADDR (MEM_DMA_ADDR + 0x40)
159 #define DMA4_RDPTH_ADDR (MEM_DMA_ADDR + 0x42)
160 #define DMA4_AAD_ADDR (MEM_DMA_ADDR + 0x44)
161 #define DMA4_ALGTH_ADDR (MEM_DMA_ADDR + 0x46)
162 #define DMA4_CTRL_ADDR (MEM_DMA_ADDR + 0x48)
163 #define DMA4_OFFSET_ADDR (MEM_DMA_ADDR + 0x4A)
164 #endif
165
166 /*--------------------------------------------------------------
167 * DMA_ALLOCDMA()
168 *--------------------------------------------------------------
169 * Parameters : none
170 * Return : none
171 * Functionality : alloc DMA channel
172 *--------------------------------------------------------------*/
173
174 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
175 // WARNING :
176 // Only the first two channels can be configured and the last two channels are forced to be controlled by the ARM
177 #define DMA_ALLOCDMA(channel0, channel1, dma_burst,priority) { \
178 * (volatile unsigned short *) DMA_CONFIG_ADDR = (dma_burst << 2) | (priority << 5); \
179 * (volatile unsigned short *) DMA_ALLOC_CONFIG_ADDR = channel0 | (channel1 << 1) | 0x000C; \
180 }
181 #else
182 #define DMA_ALLOCDMA(channel0, channel1,dma_burst,priority) (* (volatile unsigned short *) DMA_CONFIG_ADDR = channel0 | channel1 << 1 | dma_burst << 2 | priority << 5)
183 #endif
184
185 #endif /* (CHIPSET != 12)*/
186