FreeCalypso > hg > fc-magnetite
comparison doc/FCDEV3B-hardware-bug @ 474:8fbf3c0ea8b6
doc: Flash-boot-mode-hack article replaced with FCDEV3B-hardware-bug
| author | Mychaela Falconia <falcon@freecalypso.org> |
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| date | Sun, 25 Mar 2018 07:07:49 +0000 |
| parents | |
| children | 15c61c8f3166 |
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| 473:90c960bce343 | 474:8fbf3c0ea8b6 |
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| 1 Our current FCDEV3B boards exhibit a hardware bug: the reset input to the flash | |
| 2 chip is connected to Calypso's FDP output per both TI's Leonardo reference | |
| 3 schematics and Openmoko's working design, but this arrangement turns out to be | |
| 4 unsuitable for the high-capacity Spansion S71PL129NC0HFW4B flash+pSRAM chip we | |
| 5 are using, copied from Pirelli DP-L10. This hardware bug has manifested itself | |
| 6 in two different ways so far: | |
| 7 | |
| 8 * Out of the 20 boards we've built so far, on just one board there was an issue | |
| 9 where our standard Magnetite fw would have trouble booting from flash, but | |
| 10 RAM-loaded fw booted fine. Interrupting the boot process serially and having | |
| 11 the serially loaded code jump to the image in flash also worked fine. | |
| 12 Eventually it was found that the flash boot problem on that one board occurs | |
| 13 only when flash boot mode 1 is used, whereas flash boot mode 0 works fine. I | |
| 14 (Mychaela) suspect that the problem has something to do with the watchdog | |
| 15 reset that happens as part of flash boot mode 1, the FDP output behaviour | |
| 16 during that watchdog reset, and the flash chip's reaction to the latter. | |
| 17 | |
| 18 * On all of the boards there is a problem with sleep modes: when the firmware | |
| 19 is running from flash as opposed to RAM, certain sleep-wake sequences cause | |
| 20 an erratic self-reboot or a hang. It is suspected (though not proven yet) | |
| 21 that the FDP output goes low during all sleep modes, our Spansion flash chip | |
| 22 gets unhappy with the reset timing it gets subjected to, and some flash reads | |
| 23 (instruction fetches) don't work after wakeup. So far the only workable | |
| 24 solution has been to disable all sleep modes in all FCDEV3B fw builds; | |
| 25 nothing else has been successful. | |
| 26 | |
| 27 The fcdev3b-hacks directory contains two hacks that can be applied to FCDEV3B | |
| 28 firmware images (fwimage.bin builds) as xxd binary patches: | |
| 29 | |
| 30 * The first hack dating from 2017-05 patches the fw to use flash boot mode 0 | |
| 31 instead of TI's original flash boot mode 1, but after boot the FFFF:FB10 | |
| 32 register is set to put the flash and not the internal ROM at address 0, so | |
| 33 the interrupt and exception vectors go to the flash like in TI's original fw, | |
| 34 not through the internal ROM. This hack was put together for the purpose of | |
| 35 producing flashable fw images that boot without problems on that one board on | |
| 36 which flash boot mode 1 didn't work, and worked successfully for that purpose. | |
| 37 | |
| 38 * The second hack dating from 2018-03 patches the fw to not only use flash boot | |
| 39 mode 0, but also route the interrupt and exception vectors through Calypso's | |
| 40 internal ROM. I was hoping that this hack would make the sleep mode problem | |
| 41 go away by having the Calypso execute some cycles out of its internal ROM and | |
| 42 RAM before hitting the flash after wakeup, but nope, bringing up the SIM | |
| 43 interface with AT+CFUN=1 in the l1reconst config when running from flash with | |
| 44 small sleep enabled still triggers erratic misbehaviour even with this patch. | |
| 45 | |
| 46 The proper fix will be to change the PCB to not connect the flash chip's reset | |
| 47 input to FDP any more, and connect it to a pull-up resistor instead. But this | |
| 48 fix will require an expensive PCB respin, hence some experiments to test this | |
| 49 idea will need to be done first. |