fc-magnetite: src/cs/drivers/drv_app/uart/uartfax.c comparison

comparison src/cs/drivers/drv_app/uart/uartfax.c @ 695:530f71d65c20

uartfax.c: pull from Tourmaline (GTM900 RI output) In addition to the primary intent of bringing in GTM900 RI output support, pulling uartfax.c wholesale from Tourmaline also changes the initial_time argument in the two NU_Create_Timer() calls from 0 to 1. This change is required for the new version of Nucleus used in Tourmaline and Selenite (and apparently also used by TI in LoCosto), and it is harmless (no effect) for the original TCS211 version of Nucleus used in Magnetite. The new philosophical model being adopted is that Tourmaline is our new development head firmware, whereas Magnetite will now be maintained similarly to how Linux maintainers treat stable kernels: changes will be backported from Tourmaline if they are deemed appropriate for stable modem firmware.

author	Mychaela Falconia <falcon@freecalypso.org>
date	Sat, 24 Oct 2020 17:33:10 +0000
parents	005151e56328
children

comparison

equal deleted inserted replaced

-:005151e56328
+:530f71d65c20
 *     DB9   Calypso+               DB9   Calypso+
 *
 * 1   DCD   DCD      output    1   1, 6 and 4 are connected together on DB9
 * 2   RX    TX       output    2   RX    TX2       output
 * 3   TX    RX       input     3   TX    RX2       input
 * 4   DTR   DSR      input     4
 * 5   GND                      5   GND
 * 6   NC                       6
 * 7   RTS   CTS      input     7   RTS   CTS2      input
 * 8   CTS   RTS      output    8   CTS   RTS2      output
 * 9   NC                       9   NC
 *
 */
 *     DB9   Calypso                DB9   Calypso
 *
 * 1   DCD   I/O 2    output    1   1, 6 and 4 are connected together on DB9
 * 2   RX    TX       output    2   RX    TX2       output
 * 3   TX    RX       input     3   TX    RX2       input
 * 4   DTR   I/O 3    input     4
 * 5   GND                      5   GND
 * 6   NC                       6
 * 7   RTS   CTS      input     7   RTS   CTS2      input
 * 8   CTS   RTS      output    8   CTS   RTS2      output
 * 9   NC                       9   NC
 *
 */
 * 7   RTS   CTS                7   7 and 8 are connected together on DB9
 * 8   CTS   RTS                8
 * 9   NC                       9   NC
 *
 */
 #include "swconfig.cfg"
 #include "l1sw.cfg"
 #if (OP_L1_STANDALONE == 0)
 #ifdef CONFIG_TANGO_MODEM
 extern SYS_UWORD8 AI_Tango_pinmux[4];
 #endif
 /*
 * Maximal value for an unsigned 32 bits.
 */
 #define MAX_UNSIGNED_32 (4294967295)
 /*
 * TLR is used to program the RX FIFO trigger levels. FCR[7:4] are  not used.
 * No trigger level used for TX FIFO. THR_IT generated on TX FIFO empty.
 */
 #define RX_FIFO_TRIGGER_LEVEL (12 << 4)
 /*
 * 16750 addresses. Registers accessed when LCR[7] = 0.
 #define DSR_IT_BIT                (5) /* Use RESET_BIT and SET_BIT macros. */
 /*
 * Enhanced feature register.
 */
 #define ENHANCED_FEATURE_BIT (4) /* Use RESET_BIT and SET_BIT macros. */
 #define AUTO_CTS_BIT         (7) /* Transmission is halted when the CTS pin is high (inactive). */
 /*
 * Mode definition register 1.
 #define DEFAULT_GUARD_PERIOD      (1000) /* 1 second. */
 /*
 * 3 HISR are used to avoid to execute operations from the LISR.
 */
 #define RX_HISR_PRIORITY      (2)
 // NGENGE increase hisr stack otherwise overflows with multiple callbacks
 //#define RX_HISR_STACK_SIZE  (512) /* Bytes. */
 #define RX_HISR_STACK_SIZE  (768) /* Bytes. */
 #define TX_HISR_PRIORITY      (2)
 // NGENGE increase hisr stack otherwise overflows with multiple callbacks
 //#define TX_HISR_STACK_SIZE  (512) /* Bytes. */
 #define TX_HISR_STACK_SIZE  (768) /* Bytes. */
 #define V24_HISR_PRIORITY     (2)
 #define V24_HISR_STACK_SIZE (512) /* Bytes. */
 /*
 * When the break interrupt indicator (BI) is set in the line status register
 * (LSR), it indicates that the received data input was held in the low state
 * for longer than a full-word transmission time. In the FIFO mode, when a break
 /*
 * Low and high watermarks for the RX buffer. If it is enabled, the flow
 * control is activated or deactivated according to these values.
 * The high watermark value allows to copy an array filled with the RX FIFO
 * into the RX buffer.
 */
 #define RX_LOW_WATERMARK(RX_BUFFER_SIZE)  (FIFO_SIZE)
 #define RX_HIGH_WATERMARK(RX_BUFFER_SIZE) ((RX_BUFFER_SIZE) - 2 * FIFO_SIZE)
 /*
 * This macro allows to know if the RX buffer is full. It must be called only
 * from the RX HISR. If it is called from the application, the rx_in and
 * rx_fifo_in pointers may be updated if a RX interrupt occurs or if the
 * RX HISR is activated.
 */
 #define RX_BUFFER_FULL(UART)                                          \
 (((UART)->rx_in == (UART)->rx_out - 1) ||                 \
 SYS_UWORD32 base_address;
 /*
 * HISR executed from the RX/TX interrupt handler.
 */
 NU_HISR rx_hisr_ctrl_block;
 NU_HISR tx_hisr_ctrl_block;
 NU_HISR v24_hisr_ctrl_block;
 char    rx_hisr_stack[RX_HISR_STACK_SIZE];
 char    tx_hisr_stack[TX_HISR_STACK_SIZE];
 char    v24_hisr_stack[V24_HISR_STACK_SIZE];
 /*
 * 2 arrays are used to store bytes read in RX FIFO. A UART RX interrupt
 * may occur while executing RX operations in RX HISR. To avoid overwriting
 * the array in which received bytes are stored, a second array is used.
 */
 SYS_UWORD8  *rx_buffer_used_by_rx_lisr;
 SYS_UWORD8  *rx_buffer_used_by_rx_hisr;
 SYS_UWORD8  rx_fifo_byte_1[FIFO_SIZE];
 SYS_UWORD8  rx_fifo_byte_2[FIFO_SIZE];
 SYS_UWORD16 bytes_in_rx_buffer_1;
 SYS_UWORD16 bytes_in_rx_buffer_2;
 /*
 * RX and TX buffers.
 * One character is not used in each buffer to allow to know if the buffer
 * is empty or not (See macro RX_BUFFER_FULL). If buffers are empty,
 * rx_in = rx_out and tx_in = tx_out. It is impossible to use fields to
 SYS_BOOL     break_in_progress;
 NU_HISR      break_hisr_ctrl_block;
 char         break_hisr_stack[BREAK_HISR_STACK_SIZE];
 NU_TIMER     break_timer_ctrl_block;
 UNSIGNED     baudrate;
 UNSIGNED     autobauding;
 UNSIGNED     bits_per_char; /* Including start, stop and parity bits. */
 UNSIGNED     break_length;  /* In bytes. */
 UNSIGNED     time_without_character;
 /*
 * the user's Rx callback function is called if the source of interrupt was
 * the DTR interrupt regardless of the other conditions.
 * The level of DTR is saved to provide the level detected on Rx interrupt
 * or DTR interrupt in the 'state' parameter of the user's Rx callback
 * function.
 */
 SYS_BOOL   dtr_change_detected[2];
 SYS_UWORD8 dtr_level_saved[2];
 SYS_UWORD8 index_it;
 SYS_UWORD8 index_hisr;
 #endif /* BOARD 8 or 9 or 40 or 41 or CHIPSET 12 */
 SYS_BOOL         reading_suspended;
 SYS_BOOL         writing_suspended;
 SYS_BOOL         rd_call_from_hisr_in_progress;
 SYS_BOOL         wr_call_from_hisr_in_progress;
 T_reInstMode     rd_call_setup;
 0, /* 203125 baud: not supported. */
 0, /* 406250 baud: not supported. */
 0  /* 812500 baud: not supported. */
 };
 static const SYS_UWORD8 dlh[] =
 {
 0, /*   Auto baud:               */
 42, /*     75 baud.                */
 21, /*    150 baud.                */
 10, /*    300 baud.                */
 0, /* Not supported. */
 0  /* Not supported. */
 };
 /*******************************************************************************
 *
 *                          get_bytes_in_rx_buffer
 *
 * Purpose  : Gets the number of bytes in the RX buffer.
 *
 * Arguments: In : uart: Pointer on the UART structure.
 *            Out: none
 *
 }
 /*******************************************************************************
 *
 *                          get_bytes_in_tx_buffer
 *
 * Purpose  : Gets the number of bytes in the TX buffer.
 *
 * Arguments: In : uart: Pointer on the UART structure.
 *            Out: none
 *
 }
 /*******************************************************************************
 *
 *                              compute_break_time
 *
 * Purpose  : Computes a number of TDMA from 3 parameters:
 *              - baudrate,
 *              - bits per character including start bit, stop bits and parity,
 *              - number of characters.
 *            Due to the TDMA value (4.6 ms), a minimal value is sent: 2 TDMA.
 }
 /*******************************************************************************
 *
 *                          update_reading_callback
 *
 * Purpose  : Updates the sizes array and the addresses array and get and builds
 *            the state parameter defined in UAF_GetLineState to call the
 *            readOutFunc function.
 *
 * Arguments: In : uart       : Pointer on the UART structure.
 * A copy of rx_in is used because it may be updated by the interrupt
 * handler if this function is called from the application.
 */
 rx_in = uart->rx_in;
 if (uart->rx_out < rx_in) {
 fragments_number = 1;
 uart->rd_address[0] = uart->rx_out;
 uart->rd_size_after_call[1] = 0;
 bytes_in_rx_buffer = uart->rd_size_before_call[0];
 } else if (rx_in == uart->rx_out) { /* RX buffer empty. */
 fragments_number = 1;
 uart->rd_address[0] = uart->rx_out;
 uart->rd_size_before_call[0] = 0;
 uart->rd_size_after_call[0] = 0;
 uart->rd_size_before_call[1] = 0;
 uart->rd_size_after_call[1] = 0;
 bytes_in_rx_buffer = 0;
 } else {
 fragments_number = 2;
 uart->rd_address[0] = uart->rx_out;
 uart->rd_size_before_call[0] =
 uart->buffer_size + 1 - (SYS_UWORD16) (uart->rx_out -
 if (uart->flow_control_mode != fc_rts)
 state |= (((SYS_UWORD32) uart->rts_level) << SB);
 if (uart->flow_control_mode == fc_rts)
 state |= (((SYS_UWORD32) uart->rts_level) << X);
 else if ((uart->flow_control_mode == fc_xoff) &&
 (uart->tx_stopped_by_application ||
 uart->tx_stopped_by_driver))
 state |= (1 << X);
 }
 /*******************************************************************************
 *
 *                          update_writing_callback
 *
 * Purpose  : Updates the sizes array and the addresses array to call the
 *            writeInFunc function.
 *
 * Arguments: In : uart      : Pointer on the UART structure.
 *                 call_source: 0: application, 1: HISR
 * A copy of tx_out is used because it may be updated by the interrupt
 * handler if this function is called from the application.
 */
 tx_out = uart->tx_out;
 if (uart->tx_in < tx_out) {
 fragments_number = 1;
 uart->wr_address[0] = uart->tx_in;
 (SYS_UWORD16) (tx_out - uart->tx_in - 1);
 uart->wr_size_after_call[0] = uart->wr_size_before_call[0];
 uart->wr_size_before_call[1] = 0;
 uart->wr_size_after_call[1] = 0;
 } else if (tx_out == &(uart->tx_buffer[0])) {
 fragments_number = 1;
 uart->wr_address[0] = uart->tx_in;
 uart->wr_size_before_call[0] =
 uart->buffer_size -
 (SYS_UWORD16) (uart->tx_in - &(uart->tx_buffer[0]));
 uart->wr_size_after_call[0] = uart->wr_size_before_call[0];
 uart->wr_size_before_call[1] = 0;
 uart->wr_size_after_call[1] = 0;
 } else {
 fragments_number = 2;
 uart->wr_address[0] = uart->tx_in;
 uart->wr_size_before_call[0] =
 uart->buffer_size + 1 -
 (SYS_UWORD16) (uart->tx_in - &(uart->tx_buffer[0]));
 uart->wr_size_after_call[0] = uart->wr_size_before_call[0];
 uart->wr_address[1] = &(uart->tx_buffer[0]);
 uart->wr_size_before_call[1] =
 }
 /*******************************************************************************
 *
 *                                  stop_break
 *
 * Purpose  : The timer is activated to expire when a time corresponding to the
 *            sending time of 2 characters at least has elapsed. After a break,
 *            no character may be sent during this period.
 *
 * Arguments: In : id: parameter not used.
 #if ((CHIPSET != 5) && (CHIPSET != 6))
 /*
 * Disable sleep mode.
 */
 WRITE_UART_REGISTER (
 uart, IER, READ_UART_REGISTER (uart, IER) & ~IER_SLEEP);
 #endif
 /*
 }
 /*******************************************************************************
 *
 *                          hisr_start_break
 *
 * Purpose  : Enables the timer used to control the time without character.
 *
 * Arguments: In : none
 *            Out: none
 *
 }
 /*******************************************************************************
 *
 *                              stop_receiver
 *
 * Purpose  : Activates DTR or RTS or sends XOFF.
 *
 * Arguments: In : uart: Pointer on the UART structure.
 *            Out: none
 *
 * Returns  : none
 {
 #if ((CHIPSET != 5) && (CHIPSET != 6))
 /*
 * Disable sleep mode.
 */
 WRITE_UART_REGISTER (
 uart, IER, READ_UART_REGISTER (uart, IER) & ~IER_SLEEP);
 #endif
 switch (uart->flow_control_mode) {
 uart->send_xon_xoff = 1;
 /*
 * Unmask Tx interrupt.
 */
 WRITE_UART_REGISTER (
 uart, IER, READ_UART_REGISTER (uart, IER) | ETBEI);
 break;
 }
 }
 /*******************************************************************************
 *
 *                              start_receiver
 *
 * Purpose  : Deactivates DTR or RTS or sends XON.
 *
 * Arguments: In : uart: Pointer on the UART structure.
 *            Out: none
 *
 {
 #if ((CHIPSET != 5) && (CHIPSET != 6))
 /*
 * Disable sleep mode.
 */
 WRITE_UART_REGISTER (
 uart, IER, READ_UART_REGISTER (uart, IER) & ~IER_SLEEP);
 #endif
 switch (uart->flow_control_mode) {
 uart->send_xon_xoff = 1;
 /*
 * Unmask Tx interrupt.
 */
 WRITE_UART_REGISTER (
 uart, IER, READ_UART_REGISTER (uart, IER) | ETBEI);
 break;
 }
 }
 /*******************************************************************************
 *
 *                          add_esc_seq_char_in_rx_buffer
 *
 * Purpose  : Writes one escape sequence character in the RX buffer.
 *
 * Arguments: In : uart: Pointer on the UART structure.
 *            Out: none
 *
 }
 /*******************************************************************************
 *
 *                      analyze_guard_period_timer_expiration
 *
 * Purpose  : According to the state of the escape sequence detection, 1 or 2
 *            escape sequence characters may be written into the TX buffer or
 *            the escape sequence is declared as detected.
 *            If 1 or 2 escape sequence characters have been detected the
 *            guard period must not expire.
 *            expire.
 *
 * Arguments: In : id: parameter not used.
 *            Out: none
 *
 * Returns  : none
 *
 ******************************************************************************/
 static VOID
 analyze_guard_period_timer_expiration (UNSIGNED id)
 SYS_UWORD16 bytes_in_rx_buffer;
 uart = &uart_parameters;
 switch (uart->esc_seq_detection_state) {
 case ONE_CHAR_DETECTED:
 /*
 * 1 escape sequence character has been detected. The guard period has
 * ellapsed. This character is written into the TX buffer.
 */
 add_esc_seq_char_in_rx_buffer (uart);
 break;
 case TWO_CHARS_DETECTED:
 /*
 * 2 escape sequence characters have been detected. The guard period has
 * ellapsed. These characters are written into the TX buffer.
 */
 add_esc_seq_char_in_rx_buffer (uart);
 add_esc_seq_char_in_rx_buffer (uart);
 break;
 case THREE_CHARS_DETECTED:
 /*
 * 3 escape sequence characters have been detected and the guard period
 * has ellapsed. The escape sequence is detected.
 */
 uart->esc_seq_received = 1;
 *(uart->state) |= (1 << ESC);
 break;
 }
 uart->esc_seq_detection_state = NO_ESCAPE_SEQUENCE;
 /*
 * If the high watermark is reached, RTS is activated or XOFF is sent
 * according to the flow control mode.
 */
 }
 /*******************************************************************************
 *
 *                          stop_guard_period_timer
 *
 * Purpose  : Stops the timer used to detect the guard period expiration.
 *
 * Arguments: In : uart: Pointer on the UART structure.
 *            Out: none
 *
 * Returns  : none
 *
 ******************************************************************************/
 static void
 stop_guard_period_timer (t_uart *uart)
 }
 /*******************************************************************************
 *
 *                          start_guard_period_timer
 *
 * Purpose  : Starts a timer which expires if the guard period has ellapsed.
 *
 * Arguments: In : uart: Pointer on the UART structure.
 *            Out: none
 *
 * Returns  : none
 *
 ******************************************************************************/
 static void
 start_guard_period_timer (t_uart *uart)
 }
 /*******************************************************************************
 *
 *                          detect_escape_sequence
 *
 * Purpose  : The state machine used to detect an escape sequence is updated
 *            according to the array of bytes to analyse. If the state machine
 *            goes to the initial state due to a break in the sequence
 *            detection, the previous characters are put into the RX buffer.
 *
 * Arguments: In : uart: Pointer on the UART structure.
 *            Out: none
 *
 * Returns  : 0: Break in detection or a sequence has been detected.
 *            1: A sequence may be detected.
 *
 ******************************************************************************/
 static int
 switch (bytes_in_rx_buffer) {
 case 1:
 if (*rx_fifo_byte++ == uart->esc_seq_character) {
 uart->esc_seq_detection_state = ONE_CHAR_DETECTED;
 start_guard_period_timer (uart);
 detection_result = 1;
 }
 case 2:
 if ((*rx_fifo_byte++ == uart->esc_seq_character) &&
 (*rx_fifo_byte++ == uart->esc_seq_character)) {
 uart->esc_seq_detection_state = TWO_CHARS_DETECTED;
 start_guard_period_timer (uart);
 detection_result = 1;
 }
 break;
 case 3:
 if ((*rx_fifo_byte++ == uart->esc_seq_character) &&
 (*rx_fifo_byte++ == uart->esc_seq_character) &&
 (*rx_fifo_byte++ == uart->esc_seq_character)) {
 uart->esc_seq_detection_state = THREE_CHARS_DETECTED;
 start_guard_period_timer (uart);
 detection_result = 1;
 }
 break;
 default:
 /*
 * No action.
 */
 break;
 switch (bytes_in_rx_buffer) {
 case 1:
 if (*rx_fifo_byte++ == uart->esc_seq_character) {
 uart->esc_seq_detection_state = TWO_CHARS_DETECTED;
 detection_result = 1;
 }
 break;
 case 2:
 if ((*rx_fifo_byte++ == uart->esc_seq_character) &&
 (*rx_fifo_byte++ == uart->esc_seq_character)) {
 start_guard_period_timer (uart); /* Reset the timer. */
 uart->esc_seq_detection_state = THREE_CHARS_DETECTED;
 detection_result = 1;
 }
 break;
 default:
 /*
 case 1:
 if (*rx_fifo_byte++ == uart->esc_seq_character) {
 start_guard_period_timer (uart); /* Reset the timer. */
 uart->esc_seq_detection_state = THREE_CHARS_DETECTED;
 detection_result = 1;
 }
 break;
 default:
 /*
 }
 /*******************************************************************************
 *
 *                              send_break
 *
 * Purpose  : This function may only called if the TX FIFO is empty.
 *            Null characters are written in the TX FIFO. The number of bytes to
 *            write has been defined with UAF_SetLineState. Enables the break
 *            condition.
 *
 uart, IER, READ_UART_REGISTER (uart, IER) & ~IER_SLEEP);
 #endif
 WRITE_UART_REGISTER (
 uart, LCR, READ_UART_REGISTER (uart, LCR) | BREAK_CONTROL);
 #if ((CHIPSET != 5) && (CHIPSET != 6))
 /*
 * Re-enable sleep mode.
 */
 }
 /*******************************************************************************
 *
 *                              build_rx_fifo_array
 *
 * Purpose  : Reads the RX FIFO to build an array with bytes read.
 *            A byte is written in this array if no error is detected.
 *
 * Arguments: In : uart: Pointer on the UART structure.
 *            Out: none
 *
 * Returns  : The number of bytes in RX FIFO.
 volatile int x;
 x = 1;
 bytes_received = 0;
 /*
 * Switch to the other buffer.
 */
 first_byte = uart->rx_buffer_used_by_rx_lisr;
 if (first_byte == &(uart->rx_fifo_byte_1[0])) {
 first_byte = &(uart->rx_fifo_byte_2[0]);
 bytes_in_rx_buffer = &(uart->bytes_in_rx_buffer_2);
 } else {
 first_byte = &(uart->rx_fifo_byte_1[0]);
 bytes_in_rx_buffer = &(uart->bytes_in_rx_buffer_1);
 }
 current_byte = first_byte;
 if (*bytes_in_rx_buffer) {
 	/* The Rx buffer is not empty and is being used by HISR ! */
 	/* Hence stop the flow control */
 	stop_receiver (uart);
 /*
 * Reset LCR[7] (DLAB) to have access to the RBR, THR and IER registers.
 */
 WRITE_UART_REGISTER (uart, LCR, READ_UART_REGISTER (uart, LCR) & ~DLAB);
 /* Mask The Rx  and interrupt */
 WRITE_UART_REGISTER (
 uart, IER, READ_UART_REGISTER (uart, IER) &
 ~(ERBI | EDSSI));
 uart->rx_stopped_by_lisr = 1;
 	return (bytes_received);
 	}
 uart->rx_buffer_used_by_rx_lisr = first_byte;
 status = READ_UART_REGISTER (uart, LSR);
 /*
 * Build an array with the bytes contained in the RX FIFO.
 */
 /*
 * Check break detection.
 */
 if (status & BI) {
 uart->break_received = 1;
 *(uart->state) |=
 ((1 << BRK) | (MINIMAL_BREAK_LENGTH << BRKLEN));
 }
 } else /* No error */
 current_byte++;
 status = READ_UART_REGISTER (uart, LSR);
 }
 /*
 * Re-switch to the other buffer if no valid character has been received.
 */
 if (!bytes_received) {
 if (uart->rx_buffer_used_by_rx_lisr == &(uart->rx_fifo_byte_1[0]))
 uart->rx_buffer_used_by_rx_lisr = &(uart->rx_fifo_byte_2[0]);
 else
 uart->rx_buffer_used_by_rx_lisr = &(uart->rx_fifo_byte_1[0]);
 }
 if (bytes_received > uart->max_rx_fifo_level)
 uart->max_rx_fifo_level = bytes_received;
 return (bytes_received);
 }
 /*******************************************************************************
 *
 *                              empty_rx_fifo
 *
 * Purpose  : Read the RX FIFO.
 *
 * Arguments: In : uart: Pointer on the UART structure.
 *            Out: none
 *
 }
 /*******************************************************************************
 *
 *                          hisr_execute_rx_operations
 *
 * Purpose  : If an escape sequence is detected or if a break in the detection
 *            has occured RX FIFO bytes are written in the RX buffer.
 *            If the software flow control is used bytes are analyzed to know
 *            if a XON or a XOFF character is received to stop or start the
 *            transmitter.
 *            If a flow control is used and if the high watermark of the RX
 *            buffer is reached the receiver is stopped.
 *            If the RX threshold level is reached the callback mechanism is
 *            activated.
 *
 SYS_UWORD8  *current_byte;
 SYS_UWORD8  xon_xoff_detected;
 t_uart *uart;
 uart = &uart_parameters;
 /*
 * Since new characters have been received, the sleep timer is reset then
 * restarted preventing the system to enter deep-sleep for a new period of
 * time.
 */
 #if (UARTFAX_CLASSIC_DTR_DCD || (CHIPSET == 12))
 uart->index_hisr = (uart->index_hisr + 1) & 0x01; /* 0 or 1 */
 #endif
 xon_xoff_detected = 0;
 /*
 * Switch to the other buffer.
 */
 current_byte = uart->rx_buffer_used_by_rx_hisr;
 if (current_byte == &(uart->rx_fifo_byte_1[0])) {
 current_byte = &(uart->rx_fifo_byte_2[0]);
 bytes_read = uart->bytes_in_rx_buffer_2;
 } else {
 current_byte = &(uart->rx_fifo_byte_1[0]);
 bytes_read = uart->bytes_in_rx_buffer_1;
 }
 uart->rx_buffer_used_by_rx_hisr = current_byte;
 bytes_free_in_rx_buffer =
 (SYS_UWORD16) (uart->buffer_size + uart->rx_out - uart->rx_in);
 wrap_around_counter = uart->buffer_size + 1 -
 (SYS_UWORD16) (uart->rx_in - &(uart->rx_buffer[0]));
 if (uart->flow_control_mode == fc_xoff) {
 /*
 * For SW Flow Control, need to further investigate the processing
 * in order to improve the performance of the driver, and in order
 * to avoid managing the wrap around of the circular buffer each
 * time a character is copied.
 */
 while (bytes_read && bytes_free_in_rx_buffer) {
 /*
 * If the data received is XON or XOFF, the transmitter is
 * enabled (XON) or disabled (XOFF).
 #if ((CHIPSET != 5) && (CHIPSET != 6))
 /*
 * Disable sleep mode.
 */
 WRITE_UART_REGISTER (
 uart, IER, READ_UART_REGISTER (uart, IER) & ~IER_SLEEP);
 #endif
 /*
 * Unmask Tx interrupt.
 */
 WRITE_UART_REGISTER (
 uart, IER, READ_UART_REGISTER (uart, IER) | ETBEI);
 } else {
 *(uart->rx_in++) = *current_byte;
 wrap_around_counter--;
 if (!wrap_around_counter) {
 uart->rx_in = &(uart->rx_buffer[0]);
 wrap_around_counter = uart->buffer_size + 1;
 }
 bytes_free_in_rx_buffer--;
 }
 current_byte++;
 bytes_read--;
 }
 } else { /* No Flow Control or HW Flow Control */
 /*
 * Figure out the most restricting condition.
 */
 bytes_to_copy =
 Min3 (bytes_free_in_rx_buffer, wrap_around_counter, bytes_read);
 /*
 * Copy characters into the circular Rx buffer.
 */
 memcpy (uart->rx_in, current_byte, bytes_to_copy);
 /*
 * Update first the variables associated to blocking conditions:
 * if (bytes_read = 0) OR
 *    (bytes_free_in_rx_buffer = 0) => No more characters to copy.
 */
 bytes_free_in_rx_buffer	-= bytes_to_copy;
 bytes_read -= bytes_to_copy;
 wrap_around_counter -= bytes_to_copy;
 if (!wrap_around_counter)
 uart->rx_in = &(uart->rx_buffer[0]);
 else
 uart->rx_in += bytes_to_copy;
 */
 memcpy (uart->rx_in, current_byte, bytes_to_copy);
 uart->rx_in += bytes_to_copy;
 /*
 * bytes_free_in_rx_buffer not updated since not used anymore.
 */
 bytes_read -= bytes_to_copy;
 }
 else {
 	     bytes_read = 0;
 }
 } /* end if (uart->flow_control_mode == fc_xoff) */
 }
 WRITE_UART_REGISTER (uart, LCR, READ_UART_REGISTER (uart, LCR) & ~DLAB);
 /* Mask The Rx and Modem status interrupt */
 WRITE_UART_REGISTER (
 uart, IER, READ_UART_REGISTER (uart, IER) &
 ~(ERBI | EDSSI));
 if ((uart->rx_buffer_used_by_rx_hisr) == &(uart->rx_fifo_byte_1[0])) {
 	      	 uart->bytes_in_rx_buffer_1 = 0;
 	    } else {
 uart->bytes_in_rx_buffer_2 = 0;
 }
 WRITE_UART_REGISTER (uart, LCR, READ_UART_REGISTER (uart, LCR) & ~DLAB);
 /* Unmask The Rx and Modem status interrupt*/
 WRITE_UART_REGISTER (
 uart, IER, READ_UART_REGISTER (uart, IER) |
 (ERBI | EDSSI));
 if(uart->rx_stopped_by_lisr  ) {
 	if (!uart->rx_stopped_by_driver) {
 uart->rx_stopped_by_lisr = 0;
 /*
 * Reset LCR[7] (DLAB) to have access to the RBR, THR and IER registers.
 */
 WRITE_UART_REGISTER (uart, LCR, READ_UART_REGISTER (uart, LCR) & ~DLAB);
 /* UnMask The Rx interrupt */
 WRITE_UART_REGISTER (
 uart, IER, READ_UART_REGISTER (uart, IER) |
 (ERBI | EDSSI));
 start_receiver (uart);
 	}
 }
 }
 /*******************************************************************************
 *
 *                          hisr_execute_v24_operations
 *
 * Purpose  : The user's function is called if all conditions to call it are
 *            fulfiled.
 *
 * Arguments: In : none
 *            Out: none
 }
 /*******************************************************************************
 *
 *                          hisr_execute_tx_operations
 *
 * Purpose  : Writes bytes from the TX buffer to the TX FIFO.
 *            The user's function is called if all conditions to call it are
 *            fulfiled.
 *
 * Arguments: In : none
 */
 if (READ_UART_REGISTER (uart, LSR) & THRE) {
 bytes_in_tx_fifo = 0;
 /*
 * A request to send a XON/XOFF character may have been done by the
 * RX interrupt handler. The byte can be written because we are sure
 * that the TX FIFO is not full.
 */
 if (uart->send_xon_xoff) {
 if (bytes_in_tx_fifo)
 /*
 * Unmask Tx interrupt.
 */
 WRITE_UART_REGISTER (
 uart, IER, READ_UART_REGISTER (uart, IER) | ETBEI);
 else {
 }
 /*******************************************************************************
 *
 *                              read_rx_fifo
 *
 * Purpose  : Reads the RX FIFO. If the driver is enabled bytes are written in
 *            an array to be analyzed by the RX HISR.
 *
 * Arguments: In : uart: Pointer on the UART structure.
 *            Out: none
 /*
 * If the driver is disabled the RX FIFO is read to acknoledge the
 * interrupt else bytes received are written into an array which will be
 * analyzed from the RX HISR.
 */
 if (DRIVER_DISABLED (uart))
 empty_rx_fifo (uart);
 else if (build_rx_fifo_array (uart)){
 (void) NU_Activate_HISR (&(uart->rx_hisr_ctrl_block));
 	}
 }
 /*******************************************************************************
 *
 *                          check_v24_input_lines
 *
 * Purpose  : Check the V.24 input lines. According to the states of the input
 *            lines and to the flow control mode selected, the transmitter is
 *            enabled or disabled. The reading callback function is called if
 *            it is installed and if all conditions are fulfiled.
 *
 /*
 * The reading callback function has to be called. But bytes received before
 * the change of state of DTR must be copied into the RX buffer before to
 * call it.
 */
 if (READ_UART_REGISTER (uart, LSR) & DR) { /* If Rx FIFO is not empty */
 /*
 * The Rx FIFO will be read to fill one of the two buffers and the Rx
 * HISR will be activated.
 */
 uart->index_it = (uart->index_it + 1) & 0x01; /* 0 or 1 */
 uart->dtr_change_detected[uart->index_it] = 1;
 uart->dtr_level_saved[uart->index_it] = uart->dtr_level;
 read_rx_fifo (uart);
 } else
 v24_input_line_changed = 1;
 }
 #endif
 * When the hardware flow control is selected, if the RS 232 input signal is
 * deactivated (low), the transmitter is stopped.
 */
 if (uart->flow_control_mode == fc_rts) {
 if (uart->rts_level) {
 uart->tx_stopped_by_driver = 1;
 }
 else {
 uart->tx_stopped_by_driver = 0;
 #ifdef CONFIG_TARGET_GTAMODEM
 AI_ResetBit(1);
 #elif defined(CONFIG_TANGO_MODEM)
 if (AI_Tango_pinmux[0] == 0x82)
 #if ((CHIPSET != 5) && (CHIPSET != 6))
 /*
 * Disable sleep mode.
 */
 WRITE_UART_REGISTER (
 uart, IER, READ_UART_REGISTER (uart, IER) & ~IER_SLEEP);
 #endif
 /*
 }
 /*******************************************************************************
 *
 *                              fill_tx_fifo
 *
 * Purpose  : If the TX buffer is not empty, and if there is no break in
 *            progress, bytes are written into the TX FIFO until the TX FIFO is
 *            full or the TX buffer is empty. Else, if there is a break to send
 *            an all 0s character is written into the TX FIFO and a break is
 *            declared in progress to avoid to fill the TX FIFO on the next
 *            When the TX FIFO is empty and if a break is in progress, the break
 *            length is programmed: all 0s characters are written into the TX
 *            FIFO. The number of bytes has been defined previously with the
 *            UAF_SetLineState function. The break condition is enabled.
 *            When the TX FIFO and the transmitter shift register (TSR) are both
 *            empty and if a break is in progress, the break condition is
 *            disabled.
 *            When bytes are written from the TX buffer to the TX FIFO, the
 *            writing callback function is called if it is installed and if all
 *            conditions are fulfiled.
 *
 * If a break is in progress, bytes of the TX buffer are not written into
 * the TX FIFO.
 */
 if (!uart->break_in_progress)
 (void) NU_Activate_HISR (&(uart->tx_hisr_ctrl_block));
 else {
 /*
 * The break HISR is activated and the break condition is cleared.
 }
 /*******************************************************************************
 *
 *                                UAF_Init
 *
 * Purpose  : Initializes the UART hardware and installs interrupt handlers.
 *            The parameters are set to the default values:
 *               - 19200 baud,
 *               - 8 bits / character,
 *               - no parity,
 /*
 * Create the 3 HISR actived in the RX/TX and V24 interrupt handlers.
 * A return is used to simplify the code if an error occurs.
 * All stacks are entirely filled with the pattern 0xFE.
 */
 memset (&(uart->rx_hisr_stack[0]), 0xFE, RX_HISR_STACK_SIZE);
 if (NU_Create_HISR (&(uart->rx_hisr_ctrl_block),
 "UAF_Rx",
 hisr_execute_rx_operations,
 if (NU_Create_Timer (&(uart->break_timer_ctrl_block),
 "Break",
 stop_break,
 0, /* Parameter supplied to the routine: not used. */
-0, /* This parameter is set when the timer is reset. */
+1, /* This parameter is set when the timer is reset. */
 0, /* The timer expires once. */
 NU_DISABLE_TIMER) != NU_SUCCESS)
 return (FD_INTERNAL_ERR);
 if (NU_Create_Timer (&(uart->guard_period_timer_ctrl_block),
 "Esc seq",
 analyze_guard_period_timer_expiration,
 0, /* Parameter supplied to the routine: not used. */
-0, /* This parameter is set when the timer is reset. */
+1, /* This parameter is set when the timer is reset. */
 0, /* The timer expires once. */
 NU_DISABLE_TIMER) != NU_SUCCESS)
 return (FD_INTERNAL_ERR);
 * These data are used to send a break.
 * A character has: 8 data bits + 1 start bit + 1 stop bit = 10 bits.
 */
 uart->baudrate = baudrate_value[FD_BAUD_19200];
 uart->autobauding = 0;
 uart->bits_per_char = 10;
 /*
 * UART base address.
 */
 uart->base_address = base_address[uartNo];
 /*
 * Select the current array used to store received bytes.
 */
 uart->rx_buffer_used_by_rx_lisr = &(uart->rx_fifo_byte_2[0]);
 uart->rx_buffer_used_by_rx_hisr = &(uart->rx_fifo_byte_2[0]);
 /*
 * RX and TX buffers.
 */
 uart->buffer_size        = FD_MAX_BUFFER_SIZE;
 WRITE_UART_REGISTER (uart, IER, 0x00);
 /*
 * Reset UART mode configuration.
 */
 WRITE_UART_REGISTER (uart, MDR1, RESET_DEFAULT_STATE   |
 IR_SLEEP_DISABLED     |
 SIR_TX_WITHOUT_ACREG2 |
 FRAME_LENGTH_METHOD);
 /*
 * FIFO configuration.
 * EFR[4] = 1 to allow to program FCR[5:4] and MCR[7:5].
 */
 WRITE_UART_REGISTER (uart, LCR, 0xBF);
 SET_BIT (uart, EFR, ENHANCED_FEATURE_BIT);
 /*
 * Select the word length, the number of stop bits , the parity and set
 /*
 * Program the trigger levels.
 * MCR[6] must be set to 1.
 */
 SET_BIT (uart, MCR, TCR_TLR_BIT);
 WRITE_UART_REGISTER (uart, TCR, 0x0F);
 WRITE_UART_REGISTER (uart, TLR, RX_FIFO_TRIGGER_LEVEL);
 RESET_BIT (uart, MCR, TCR_TLR_BIT);
 * Force the generation of THR_IT on TX FIFO empty: SCR[3] = 1.
 */
 WRITE_UART_REGISTER (
 uart, SCR, READ_UART_REGISTER (uart, SCR) | TX_EMPTY_CTL_IT);
 /*
 * Program the FIFO control register. Bit 0 must be set when other FCR bits
 * are written to or they are not programmed.
 * FCR is a write-only register. It will not be modified.
 */
 WRITE_UART_REGISTER (uart, LCR, READ_UART_REGISTER (uart, LCR) & ~DLAB);
 /*
 * Select UART mode.
 */
 WRITE_UART_REGISTER (uart, MDR1, UART_MODE             |
 IR_SLEEP_DISABLED     |
 SIR_TX_WITHOUT_ACREG2 |
 FRAME_LENGTH_METHOD);
 /*
 * On C & D-Sample, 2 I/O are used to control DCD and DTR on UART Modem.
 * DCD: I/O 2 (output)
 * DTR: I/O 3 (input)
 */
 #define EXTENDED_MCU_REG (0xFFFEF006) /* Extended MCU register       */
 #define ASIC_CONFIG_REG  (0xFFFEF008) /* Asic Configuration register */
 #define IO_DTR (10) /* I/O 3; bit 10 of Asic Configuration register */
 #define IO_DCD ( 6) /* I/O 2; bit 6 of Extended MCU register        */
 /*
 * Select I/O for DTR and configure it as input.
 * An interrupt is used to detect a change of state of DTR. Falling edge
 * or rising edge is selected according to the state of DTR.
 */
 #ifdef CONFIG_TANGO_MODEM
 if (AI_Tango_pinmux[1] & 0x80) {
 #endif
 *((volatile SYS_UWORD16 *) ASIC_CONFIG_REG) &= ~(1 << IO_DTR);
 AI_ConfigBitAsInput (ARMIO_DTR);
 if (uart->dtr_level)
 AI_SelectIOForIT (ARMIO_DTR, ARMIO_FALLING_EDGE);
 else
 AI_SelectIOForIT (ARMIO_DTR, ARMIO_RISING_EDGE);
 AI_UnmaskIT (ARMIO_MASKIT_GPIO);
 #ifdef CONFIG_TANGO_MODEM
 } else
 uart->dtr_level = 0;
 #endif
 /*
 * Reset the 2 indexes of the circular buffer of 2 elements.
 * The circular buffer does not need to be initialized.
 */
 uart->index_it = 0;
 uart->index_hisr = 0;
 #elif (CHIPSET == 12)
 /*
 * DCD and DTR are directly handled by Calypso+.
 /*
 * Reset the 2 indexes of the circular buffer of 2 elements.
 * The circular buffer does not need to be initialized.
 */
 uart->index_it = 0;
 uart->index_hisr = 0;
 #endif /* BOARD == 8, 9, 40 or 41, CHIPSET == 12 */
 /*
 * Unmask RX interrupt and the modem status interrupt.
 */
 WRITE_UART_REGISTER (uart, IER, ERBI | EDSSI);
 }
 /*******************************************************************************
 *
 *                               UAF_Enable
 *
 * Purpose  : The functionalities of the UART driver are disabled or enabled.
 *            In the deactivated state, all information about the communication
 *            parameters should be stored and recalled if the driver is again
 *            enabled. When the driver is enabled the RX and TX buffers are
 *            cleared.
 return (FD_NOT_SUPPORTED);
 /*
 * There is no case where FD_INTERNAL_ERR may be returned.
 */
 uart = &uart_parameters;
 if (enable) {
 uart->rx_stopped_by_driver = 0;
 ENABLE_DRIVER (uart);
 start_receiver (uart);
 } else {
 }
 /*******************************************************************************
 *
 *                            UAF_SetComPar
 *
 * Purpose  : Sets up the communication parameters: baud rate, bits per
 *            character, number of stop bits, parity.
 *
 * Arguments: In : uartNo  : Used UART.
 *                 baudrate: Used baud rate.
 #endif
 /*
 * Reset UART mode configuration.
 */
 WRITE_UART_REGISTER (uart, MDR1, RESET_DEFAULT_STATE   |
 IR_SLEEP_DISABLED     |
 SIR_TX_WITHOUT_ACREG2 |
 FRAME_LENGTH_METHOD);
 /*
 * FIFO configuration.
 * EFR[4] = 1 to allow to program FCR[5:4] and MCR[7:5].
 */
 WRITE_UART_REGISTER (uart, LCR, 0xBF);
 SET_BIT (uart, EFR, ENHANCED_FEATURE_BIT);
 /*
 * Select the word length, the number of stop bits , the parity and set
 uart->autobauding = (baudrate == FD_BAUD_AUTO);  /* if autobauding enable trigger */
 uart->bits_per_char = 1; /* Start bit. */
 mcr_value = DLAB;
 if (bpc == bpc_7) {
 mcr_value |= WLS_7;
 uart->bits_per_char += 7;
 } else {
 /*
 * Program the trigger levels.
 * MCR[6] must be set to 1.
 */
 SET_BIT (uart, MCR, TCR_TLR_BIT);
 WRITE_UART_REGISTER (uart, TCR, 0x0F);
 WRITE_UART_REGISTER (uart, TLR, RX_FIFO_TRIGGER_LEVEL);
 RESET_BIT (uart, MCR, TCR_TLR_BIT);
 * Force the generation of THR_IT on TX FIFO empty: SCR[3] = 1.
 */
 WRITE_UART_REGISTER (
 uart, SCR, READ_UART_REGISTER (uart, SCR) | TX_EMPTY_CTL_IT);
 /*
 * Program the FIFO control register. Bit 0 must be set when other FCR bits
 * are written to or they are not programmed.
 * FCR is a write-only register. It will not be modified.
 */
 WRITE_UART_REGISTER (uart, LCR, READ_UART_REGISTER (uart, LCR) & ~DLAB);
 /*
 * Select UART mode.
 */
 WRITE_UART_REGISTER (uart, MDR1,  ((baudrate==FD_BAUD_AUTO)?
 UART_MODE_AUTOBAUDING:
 UART_MODE)             |
 IR_SLEEP_DISABLED     |
 SIR_TX_WITHOUT_ACREG2 |
 #if UARTFAX_CLASSIC_DTR_DCD
 /*
 * Read the state of DTR and select the edge.
 */
 #ifdef CONFIG_TANGO_MODEM
 if (AI_Tango_pinmux[1] & 0x80) {
 #endif
 uart->dtr_level = AI_ReadBit (ARMIO_DTR);
 if (uart->dtr_level)
 AI_SelectIOForIT (ARMIO_DTR, ARMIO_FALLING_EDGE);
 else
 AI_SelectIOForIT (ARMIO_DTR, ARMIO_RISING_EDGE);
 AI_UnmaskIT (ARMIO_MASKIT_GPIO);
 #ifdef CONFIG_TANGO_MODEM
 } else
 uart->dtr_level = 0;
 #endif
 uart->dtr_level = 1;
 #endif
 #if ((CHIPSET == 5) || (CHIPSET == 6))
 /*
 * Unmask RX and TX interrupts and the modem status interrupt.
 */
 WRITE_UART_REGISTER (uart, IER, ERBI | ETBEI | EDSSI);
 #elif (CHIPSET == 12)
 /*
 * Unmask RX and TX interrupts and the modem status interrupt...
 */
 WRITE_UART_REGISTER (uart, IER, ERBI | ETBEI | EDSSI);
 /*
 * ... Then, unmask DSR interrupt...
 */
 	ENABLE_DSR_INTERRUPT (uart);
 /*
 * ... And finally allow sleep mode.
 */
 /*
 WRITE_UART_REGISTER (uart, IER, READ_UART_REGISTER (uart, IER) | IER_SLEEP);
 */
 #else
 /*
 * Unmask RX and TX interrupts and the modem status interrupt
 * and allow sleep mode.
 */
 /* BELOW LINES WERE COMMENTED TO DISABLE SLEEP MODE IN DRIVER */
 /* WRITE_UART_REGISTER (uart, IER, ERBI | ETBEI | EDSSI | IER_SLEEP);*/
 }
 /*******************************************************************************
 *
 *                            UAF_SetBuffer
 *
 * Purpose  : Sets up the size of the circular buffers to be used in the UART
 *            driver. This function may be called only if the UART is disabled
 *            with UAF_Enable.
 *
 * Arguments: In : uartNo     : Used UART.
 (txThreshold > FD_MAX_BUFFER_SIZE))
 result = FD_NOT_SUPPORTED;
 else {
 uart = &uart_parameters;
 if (!DRIVER_DISABLED (uart))
 result = FD_INTERNAL_ERR;
 else if (RX_HIGH_WATERMARK (bufSize) < RX_LOW_WATERMARK (bufSize))
 result = FD_NOT_SUPPORTED;
 else {
 uart->buffer_size = bufSize;
 uart->rx_threshold_level = rxThreshold;
 uart->tx_threshold_level = txThreshold;
 result = FD_OK;
 }
 /*******************************************************************************
 *
 *                             UAF_SetFlowCtrl
 *
 * Purpose  : Changes the flow control mode of the UART driver.
 *            If a flow control is activated, DTR is activated or XOFF is sent
 *            if the RX buffer is not able to store the received characters else
 *            DTR is deactivated or XON is sent.
 *
 if (fcMode == fc_dtr)
 result = FD_NOT_SUPPORTED;
 else {
 uart = &uart_parameters;
 uart->tx_stopped_by_driver = 0;
 uart->xon_character = XON;
 uart->xoff_character = XOFF;
 uart->flow_control_mode = fcMode;
 #if ((CHIPSET != 5) && (CHIPSET != 6))
 uart, IER, READ_UART_REGISTER (uart, IER) & ~IER_SLEEP);
 #endif
 WRITE_UART_REGISTER (
 uart, MCR, READ_UART_REGISTER (uart, MCR) | MRTS);
 #if ((CHIPSET != 5) && (CHIPSET != 6))
 /*
 * Re-enable sleep mode.
 */
 /* BELOW LINES WERE COMMENTED TO DISABLE SLEEP MODE IN DRIVER */
 } else if (!DRIVER_DISABLED (uart)) {
 uart->rx_stopped_by_driver = 0;
 start_receiver (uart);
 }
 } else {
 uart->rx_stopped_by_driver = 0;
 uart->tx_stopped_by_driver = 0;
 }
 result = FD_OK;
 }
 /*******************************************************************************
 *
 *                               UAF_SetEscape
 *
 * Purpose  : To return to the command mode at the ACI while a data connection
 *            is established, an escape sequence has to be detected.
 *            To distinguish between user data and the escape sequence a
 *            defined guard period is necessary before and after this sequence.
 *
 }
 /*******************************************************************************
 *
 *                              UAF_InpAvail
 *
 * Purpose  : Returns the number of characters available in the RX buffer of the
 *            driver. If the driver is disabled the function returns 0.
 *
 * Arguments: In : uartNo: Used UART.
 *            Out: none
 }
 /*******************************************************************************
 *
 *                             UAF_OutpAvail
 *
 * Purpose  : Returns the number of free characters in TX buffer of the driver.
 *            If the driver is disabled the function returns 0.
 *
 * Arguments: In : uartNo: Used UART.
 *            Out: none
 {
 #if ((CHIPSET != 5) && (CHIPSET != 6))
 /*
 * Disable sleep mode.
 */
 WRITE_UART_REGISTER (
 uart, IER, READ_UART_REGISTER (uart, IER) & ~IER_SLEEP);
 #endif
 /*
 * Unmask Tx interrupt.
 */
 WRITE_UART_REGISTER (
 uart, IER, READ_UART_REGISTER (uart, IER) | ETBEI);
 }
 }
 }
 /*******************************************************************************
 *
 *                             UAF_EnterSleep
 *
 * Purpose  : Checks if UART is ready to enter Deep Sleep. If ready, enables
 *            wake-up interrupt.
 *
 * Arguments: In : uartNo: Used UART.
 *            Out: none
 UAF_EnterSleep (T_fd_UartId uartNo)
 {
 t_uart              *uart;
 SYS_BOOL            deep_sleep;
 volatile SYS_UWORD8 status;
 /*
 * Check UART number.
 * A return is used to simplify the code.
 * UART IrDA (UAF_UART_0) can't be used for F&D on Ulysse because hardware
 * flow control is not supported.
 #if ((CHIPSET != 5) && (CHIPSET != 6))
 /*
 * Disable sleep mode.
 */
 WRITE_UART_REGISTER (
 uart, IER, READ_UART_REGISTER (uart, IER) & ~IER_SLEEP);
 #endif
 #if (CHIPSET == 12)
 }
 /*******************************************************************************
 *
 *                              UAF_WakeUp
 *
 * Purpose  : Wakes up UART after Deep Sleep.
 *
 * Arguments: In : uartNo: Used UART.
 *            Out: none
 *
 T_FDRET
 UAF_WakeUp (T_fd_UartId uartNo)
 {
 t_uart *uart;
 /*
 * Check UART number.
 * A return is used to simplify the code.
 * UART IrDA (UAF_UART_0) can't be used for F&D on Ulysse because hardware
 * flow control is not supported.
 #if ((CHIPSET != 5) && (CHIPSET != 6))
 /*
 * Allow sleep mode.
 */
 /* BELOW LINES WERE COMMENTED TO DISABLE SLEEP MODE IN DRIVER */
 /*
 WRITE_UART_REGISTER (
 uart, IER, READ_UART_REGISTER (uart, IER) | IER_SLEEP);
 */
 #endif
 return (FD_OK);
 }
 /*******************************************************************************
 *
 *                              UAF_ReadData
 *
 * Purpose  : To read the received characters out of the RX buffer the address
 *            of a function is passed. If characters are available, the driver
 *            calls this function and pass the address and the amount of
 *            readable characters. Because the RX buffer is circular, the
 *            callback function may be called with more than one address of
 *                              source    : Array which contains the addresses
 *                                          of the fragments.
 *                              size      : Array which contains the sizes of
 *                                          each fragments.
 *                              state     : The state parameter is the status
 *                                          of the V.24 lines and the break /
 *                                          escape detection. The state
 *                                          parameter is described in the
 *                                          specification of UAF_GetLineState.
 *            Out: none
 *
 uart->readOutFunc = readOutFunc;
 uart->reading_suspended = 1;
 result = FD_SUSPENDED;
 } else {
 /*
 * The previous callback function is deinstalled.
 */
 uart->rd_call_setup = rm_noInstall;
 uart->reading_suspended = 0;
 result = 0; /* 0 byte read. */
 }
 }
 /*******************************************************************************
 *
 *                              UAF_WriteData
 *
 * Purpose  : To write characters into the TX buffer the address of a function
 *            is passed. If free space is available in the buffer, the driver
 *            calls this function and passes the destination address and the
 *            amount of space. Because the TX buffer is circular, the callback
 *            function may be called with more than one address of buffer
 *            UAF_SetBuffer). If no suspension is necessary the function returns
 *            the number of processed bytes.
 *
 * Arguments: In : uartNo     : Used UART.
 *                 suspend    : mode of suspension in case of TX buffer empty.
 *                 writeInFunc: Callback function.
 *                              cldFromIrq: The driver sets this parameter to 1
 *                                          if the call-back function is called
 *                                          from an interrupt service routine.
 *                              reInstall : The callback function sets this
 *                                          parameter to rm_reInstall if the
 *      - the flow control is not activated,
 * unmask the TX empty interrupt to be able to send characters.
 */
 if (!uart->break_to_send &&
 !uart->tx_stopped_by_driver)
 {
 #if ((CHIPSET != 5) && (CHIPSET != 6))
 /*
 * Disable sleep mode.
 */
 WRITE_UART_REGISTER (
 uart, IER, READ_UART_REGISTER (uart, IER) & ~IER_SLEEP);
 #endif
 /*
 * Unmask Tx interrupt.
 */
 WRITE_UART_REGISTER (
 uart, IER, READ_UART_REGISTER (uart, IER) | ETBEI);
 }
 result = (T_FDRET) bytes_written;
 uart->writeInFunc = writeInFunc;
 uart->writing_suspended = 1;
 result = FD_SUSPENDED;
 } else {
 /*
 * The previous callback function is deinstalled.
 */
 uart->wr_call_setup = rm_noInstall;
 uart->writing_suspended = 0;
 result = 0;
 }
 }
 /*******************************************************************************
 *
 *                              UAF_StopRec
 *
 * Purpose  : If a flow control mode is set, this function tells the terminal
 *            equipment that no more data can be received.
 *            XON/XOFF: XOFF is sent.
 *            DTR/DSR : DTR is desactivated.
 *            RTS/CTS : RTS is deactivated.
 }
 /*******************************************************************************
 *
 *                              UAF_StartRec
 *
 * Purpose  : If a flow control mode is set, this function tells the terminal
 *            equipment that the receiver is again able to receive more data.
 *            If the buffer has already reached the high water mark the driver
 *            sends the signal only if the buffer drains to a low water mark.
 *            XON/XOFF: XON is sent.
 *            FD_NOT_SUPPORTED: Wrong UART number.
 *            FD_INTERNAL_ERR : Internal problem with the hardware.
 *
 ******************************************************************************/
 T_FDRET
 UAF_StartRec (T_fd_UartId uartNo)
 {
 t_uart *uart;
 /*
 }
 /*******************************************************************************
 *
 *                            UAF_GetLineState
 *
 * Purpose  : Returns the state of the V.24 lines, the flow control state and
 *            the result of the break/escape detection process as a bit field.
 *
 * Arguments: In : uartNo: Used UART.
 *            Out: state : State of the V.24 lines, the flow control state and
 *                         the result of the break/escape sequence detection
 *                         process as a bit field.
 *
 * Returns  : FD_OK           : Successful operation.
 *            FD_NOT_SUPPORTED: Wrong UART number.
 *            FD_NOT_READY    : The function is called while the callback of
 *                              the readOutFunc function is activated and still
 *                              not terminated.
 *            FD_INTERNAL_ERR : Internal problem with the hardware.
 *
 ******************************************************************************/
 /*
 * The field state_2 is used when state_1 is set to 0 to avoid to
 * lose events detected in the RX interrupt handler.
 * Fields BRK and BRKLEN are set when a break is detected.
 * The field ESC is set when an escape sequence is detected.
 */
 *state = uart->state_2;
 uart->state_2 = 0;
 uart->state = &(uart->state_2);
 *state |= uart->state_1;
 uart->state_1 = 0;
 uart->state = &(uart->state_1);
 *state |= ((((SYS_UWORD32) uart->rts_level) << RTS) |
 #if (UARTFAX_CLASSIC_DTR_DCD || (CHIPSET == 12))
 (((SYS_UWORD32) uart->dtr_level) << DTR) |
 #endif
 (((SYS_UWORD32) (uart->tx_stopped_by_application  |
 uart->tx_stopped_by_driver)) << TXSTP) |
 (((SYS_UWORD32) (uart->rx_stopped_by_application  |
 uart->rx_stopped_by_driver)) << RXSTP) |
 (((SYS_UWORD32) (uart->buffer_size -
 get_bytes_in_rx_buffer (uart))) << RXBLEV));
 /*
 * Fields SA, SB and X are set according to the flow control:
 *
 *       None    RTS/CTS    XON/XOFF
 * SA    DTR     DTR        DTR
 if (uart->flow_control_mode != fc_rts)
 *state |= (((SYS_UWORD32) uart->rts_level) << SB);
 if (uart->flow_control_mode == fc_rts)
 *state |= (((SYS_UWORD32) uart->rts_level) << X);
 else if ((uart->flow_control_mode == fc_xoff) &&
 (uart->tx_stopped_by_application ||
 uart->tx_stopped_by_driver))
 *state |= (1 << X);
 }
 /*******************************************************************************
 *
 *                            UAF_SetLineState
 *
 * Purpose  : Sets the states of the V.24 status lines according to the bit
 *            field of the parameter state.
 *
 * Arguments: In : uartNo: Used UART.
 *                 state : Bit field. Only the signals which are marked with
 if (mask & (1 << SA))
 #else
 if ((mask & (1 << SA)) || (mask & (1 << DCD)))
 #endif
 return (FD_NOT_SUPPORTED); /* Return used to simplify the code */
 /*
 * Check if a break has to be sent.
 */
 uart->break_length = (UNSIGNED) ((state >> BRKLEN) & 0xFF);
 * The CTS field is ignored if the X bit in the mask is set. In this case
 * the X bit controls CTS.
 */
 if (mask & (1 << CTS)) {
 if (uart->flow_control_mode != fc_rts) {
 /*
 * As the RTS/CTS flow control is not selected, the X bit does not
 * control CTS. CTS needs only to be activated or deactivated
 * according to the value of the CTS field.
 */
 * is null. Then the CTS bit controls CTS and the receiver must be
 * stopped or started according to the state of the CTS bit.
 * The receiver is started only if it was not stopped by the driver
 * and if it was stopped by the application.
 */
 if (state & (1 << CTS)) {
 if (!uart->rx_stopped_by_application) {
 if (!uart->rx_stopped_by_driver)
 stop_receiver (uart);
 uart->rx_stopped_by_application = 1;
 }
 } else {
 if ((!uart->rx_stopped_by_driver) &&
 uart->rx_stopped_by_application)
 start_receiver (uart);
 uart->rx_stopped_by_application = 0;
 AI_SetBit(1);
 }
 }
 #endif	/* Tango modem */
+#ifdef CONFIG_TARGET_GTM900
+if (mask & (1 << RI)) {
+if (state & (1 << RI)) {
+/* Turn on RI */
+AI_ResetBit(0);
+} else {
+/* Turn off RI */
+AI_SetBit(0);
+}
+}
+#endif	/* GTM900 modem */
 if ((mask & (1 << X)) &&
 (uart->flow_control_mode != fc_none)) {
 if (state & (1 << X)) {
 if (!uart->rx_stopped_by_application) {
 if (!uart->rx_stopped_by_driver)
 stop_receiver (uart);
 uart->rx_stopped_by_application = 1;
 }
 } else {
 /*
 * The receiver is started only if it is not stopped by the driver
 * and if it is stopped by the application.
 */
 #if ((CHIPSET != 5) && (CHIPSET != 6))
 /*
 * Re-enable sleep mode.
 */
 /* BELOW LINES WERE COMMENTED TO DISABLE SLEEP MODE IN DRIVER */
 /*
 WRITE_UART_REGISTER (
 uart, IER, READ_UART_REGISTER (uart, IER) | IER_SLEEP);
 */
 #endif
 }
 /*******************************************************************************
 *
 *                           UAF_InterruptHandler
 *
 * Purpose  : Interrupt handler.
 *
 * Arguments: In : uart_id         : origin of interrupt
 *                 interrupt_status: source of interrupt
 *            Out: none
 }
 /*******************************************************************************
 *
 *                              UAF_CheckXEmpty
 *
 * Purpose  : Checks the empty condition of the Transmitter.
 *
 * Arguments: In : uartNo: Used UART.
 *            Out: none
 *
 /*
 * There is no case where FD_INTERNAL_ERR may be returned.
 	 */
 result = FD_OK;
 uart = &uart_parameters;
 status = READ_UART_REGISTER (uart, LSR);
 /*
 * Checks if:
 void
 UAF_DTRInterruptHandler (void)
 {
 t_uart *uart;
 uart = &uart_parameters;
 /*
 * Read the state of DTR and change the edge to detect the next change
 * of DTR.
 */
 uart->dtr_level = AI_ReadBit (ARMIO_DTR);
 if (uart->dtr_level)
 	{
 AI_SelectIOForIT (ARMIO_DTR, ARMIO_FALLING_EDGE);
 	 if (uart->flow_control_mode != fc_dtr  && uart->baudrate == baudrate_value[FD_BAUD_AUTO])
 UAF_SetComPar (UAF_UART_1, FD_BAUD_AUTO, bpc_8, sb_1, pa_none);
 }
 else
 AI_SelectIOForIT (ARMIO_DTR, ARMIO_RISING_EDGE);
 /*
 * The reading callback function has to be called. But bytes received before
 * the change of state of DTR must be copied into the RX buffer before to
 * call it.
 */
 if (READ_UART_REGISTER (uart, LSR) & DR) { /* If Rx FIFO is not empty */
 /*
 * The Rx FIFO will be read to fill one of the two buffers and the Rx
 * HISR will be activated.
 */
 uart->index_it = (uart->index_it + 1) & 0x01; /* 0 or 1 */
 uart->dtr_change_detected[uart->index_it] = 1;
 uart->dtr_level_saved[uart->index_it] = uart->dtr_level;
 read_rx_fifo (uart);
 } else
 (void) NU_Activate_HISR (&(uart->v24_hisr_ctrl_block));
 }
 #endif /* BOARD 8 or 9 or 40 or 41 */
 #ifdef SERIAL_DYNAMIC_SWITCH
 /*******************************************************************************
 *
 *                                UAF_Exit
 *
 * Purpose  :
 *
 * Arguments: In : uartNo: Used UART.
 *            Out: none
 *
 * Returns  : FD_OK           : Successful operation.

FreeCalypso > hg > fc-magnetite

comparison src/cs/drivers/drv_app/uart/uartfax.c @ 695:530f71d65c20