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comparison src/cs/layer1/cfile/l1_pwmgr.c @ 69:50a15a54801e

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src/cs/layer1: import from tcs211-l1-reconst project
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 01 Oct 2016 23:45:38 +0000
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children daddb933047d
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68:838717193e09 69:50a15a54801e
1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 * L1_PWMGR.C
4 *
5 * Filename l1_pwmgr.c
6 * Copyright 2003 (C) Texas Instruments
7 *
8 ************* Revision Controle System Header *************/
9
10 #define L1_PWMGR_C
11 //#pragma DUPLICATE_FOR_INTERNAL_RAM_START
12
13 #include "timer/timer2.h"
14 #include "armio/armio.h"
15
16 //omaps00090550 #include "l1_macro.h"
17 #include "l1_confg.h"
18
19 #if (OP_L1_STANDALONE == 1)
20 #include "uart/serialswitch_core.h"
21 #else
22 #include "uart/serialswitch.h"
23 #endif
24
25 #if (OP_L1_STANDALONE == 0)
26 #include "sim/sim.h"
27 #include "rv_swe.h"
28 #endif
29
30
31 #if (CODE_VERSION == SIMULATION)
32 #include "l1_types.h"
33 #include "l1_const.h"
34
35 #if (CHIPSET == 12) || (CHIPSET == 15)
36 #include "inth/sys_inth.h"
37 #include "sys_dma.h"
38 #include "ulpd.h"
39 #include "clkm.h"
40
41 // typedef volatile unsigned short REG_UWORD16; //omaps00090550
42 #define REG16(A) (*(REG_UWORD16*)(A))
43
44 #else
45 #include "inth/iq.h"
46 #endif
47
48 #if TESTMODE
49 #include "l1tm_defty.h"
50 #endif // TESTMODE
51
52 #if (AUDIO_TASK == 1)
53 #include "l1audio_const.h"
54 #include "l1audio_cust.h"
55 #include "l1audio_defty.h"
56 #endif // AUDIO_TASK
57
58 #if (L1_GTT == 1)
59 #include "l1gtt_const.h"
60 #include "l1gtt_defty.h"
61 #endif
62
63 #if (L1_MP3 == 1)
64 #include "l1mp3_defty.h"
65 #endif
66
67 #if (L1_MIDI == 1)
68 #include "l1midi_defty.h"
69 #endif
70 //ADDED FOR AAC
71 #if (L1_AAC == 1)
72 #include "l1aac_defty.h"
73 #endif
74 #include "l1_defty.h"
75 #include "l1_varex.h"
76 #include "l1_tabs.h"
77 #include "cust_os.h"
78 #include "l1_msgty.h"
79 #include "l1_proto.h"
80 #include "ulpd.h"
81 #include "l1_trace.h"
82
83 #if L1_GPRS
84 #include "l1p_cons.h"
85 #include "l1p_msgt.h"
86 #include "l1p_deft.h"
87 #include "l1p_vare.h"
88 #endif // L1_GPRS
89
90 #include <stdio.h>
91 #include "sim_cfg.h"
92 #include "sim_cons.h"
93 #include "sim_def.h"
94 #include "sim_var.h"
95 //omaps00090550
96 #include "nucleus.h"
97
98 extern NU_TASK L1S_task;
99 STATUS status;
100
101
102
103 #else // NO SIMULATION
104
105
106
107 #include "l1_types.h"
108 #include "l1_const.h"
109
110 #include "abb/abb.h"
111 #include "dma/sys_dma.h"
112
113 #if (OP_BT == 1)
114 #include "hci_ll_simul.h"
115 #endif
116
117 #if TESTMODE
118 #include "l1tm_defty.h"
119 #endif // TESTMODE
120
121 #if (AUDIO_TASK == 1)
122 #include "l1audio_const.h"
123 #include "l1audio_cust.h"
124 #include "l1audio_defty.h"
125 #endif // AUDIO_TASK
126
127 #if (L1_GTT == 1)
128 #include "l1gtt_const.h"
129 #include "l1gtt_defty.h"
130 #endif
131
132 #if (L1_MP3 == 1)
133 #include "l1mp3_defty.h"
134 #endif
135
136 #if (L1_MIDI == 1)
137 #include "l1midi_defty.h"
138 #endif
139 //ADDED FOR AAC
140 #if (L1_AAC == 1)
141 #include "l1aac_defty.h"
142 #endif
143 #include "l1_defty.h"
144 #include "l1_varex.h"
145 #include "l1_tabs.h"
146 #include "sys_types.h"
147 #include "tpudrv.h"
148 #include "cust_os.h"
149 #include "l1_msgty.h"
150 #include "l1_proto.h"
151 #include "l1_trace.h"
152 #include "timer/timer.h"
153
154 #if (CHIPSET == 12) || (CHIPSET == 15)
155 #include "timer/timer_sec.h"
156 #include "inth/sys_inth.h"
157
158 /* FreeCalypso: massive #if (CHIPSET == 15) chunk removed */
159
160 #else //(CHIPSET == 12) || (CHIPSET == 15)
161 #include "inth/iq.h"
162 #include "inth/inth.h"
163 #endif
164 // #include "timer1.h"
165 #include "ulpd/ulpd.h"
166 #include "clkm/clkm.h"
167 #include "memif/mem.h"
168 #if L2_L3_SIMUL
169 #include "hw_debug.h"
170 #endif
171
172 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1)
173 #include "csmi/sleep.h"
174 #endif // OP_WCP
175 #if (W_A_CALYPSO_PLUS_SPR_19599 == 1)
176 #include "sys_memif.h"
177 #endif
178
179 #if (GSM_IDLE_RAM != 0)
180 #if (OP_L1_STANDALONE == 1)
181 #include "csmi_simul.h"
182 #else
183 #include "csmi/csmi.h"
184 #endif
185 #endif
186
187 #if (CHIPSET == 15)
188 #include "drp_api.h"
189 #endif
190
191 #endif // NO SIMULATION
192
193 #if (CODE_VERSION != SIMULATION)
194 // for PTOOL compatibility
195 extern void INT_DisableIRQ(void);
196 extern void INT_EnableIRQ(void);
197 extern void l1dmacro_RF_sleep(void);
198 extern void l1dmacro_RF_wakeup(void);
199 WORD32 l1s_get_HWTimers_ticks(void);
200
201 // file timer1.h
202 SYS_UWORD16 Dtimer1_Get_cntlreg(void);
203 void Dtimer1_AR(unsigned short Ar);
204 void Dtimer1_PTV(unsigned short Ptv);
205 void Dtimer1_Clken(unsigned short En);
206 void Dtimer1_Start (unsigned short startStop);
207 void Dtimer1_Init_cntl (SYS_UWORD16 St, SYS_UWORD16 Reload, SYS_UWORD16 clockScale, SYS_UWORD16 clkon);
208 SYS_UWORD16 Dtimer1_WriteValue (SYS_UWORD16 value);
209 SYS_UWORD16 Dtimer1_ReadValue (void);
210 #endif
211
212 void l1s_wakeup(void);
213 BOOL l1s_compute_wakeup_ticks(void);
214 void l1s_recover_Frame(void);
215 UWORD8 Cust_recover_Os(void);
216 void l1s_recover_HWTimers(void);
217 UWORD8 Cust_check_system(void);
218 void f_arm_sleep_cmd(UWORD8 d_sleep_mode);
219
220 //#if (TRACE_TYPE == 2) || (TRACE_TYPE == 3)
221 extern void L1_trace_string(char *s);
222 extern void L1_trace_char (char s);
223 //#endif
224 extern UWORD16 slp_debug_flag;
225
226 #if (GSM_IDLE_RAM != 0)
227 extern void l1s_trace_mftab(void);
228 #endif
229
230 #if (CODE_VERSION != SIMULATION) && (CHIPSET == 15)
231 extern T_DRP_REGS_STR *drp_regs;
232 #endif
233
234 #if L1_GPRS
235 WORD32 l1s_get_next_gauging_in_Packet_Idle(void);
236 #endif
237 //#pragma DUPLICATE_FOR_INTERNAL_RAM_END
238
239 #if !((MOVE_IN_INTERNAL_RAM == 1) && (GSM_IDLE_RAM !=0)) // MOVE TO INTERNAL MEM IN CASE GSM_IDLE_RAM enabled
240 //#pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_START // KEEP IN EXTERNAL MEM otherwise
241
242 /************************************************************/
243 /* Macros for power management */
244 /************************************************************/
245 #define MIN(min, operand1) \
246 if (operand1 <= min) min = operand1;
247
248 // ex: RATIO T32khz/T4.33Mhz = 132.2428385417
249 // => root = integer part of the ratio
250 // = 132
251 // => frac = fractionnal part of the ratio multiplied by 65536 rounded to make it integer
252 // = 0.2428385417 * 65536 (Cf. ULPD specification)
253 // = 0.2428385417 * 2^16
254 // = 15914.66666689 = 15914
255
256 #define RATIO(HF,LF, root, frac) \
257 root = (UWORD32)(HF/LF); \
258 frac = (UWORD32)(((HF - (root*LF)) << 16) / LF);
259
260 // previous ratio with frac + 0.5
261 #if 0 /* original LoCosto code */
262 #define RATIO2(HF,LF, root, frac) \
263 if(LF){ \
264 root = (UWORD32)(HF/LF); \
265 frac = (UWORD32)((((HF - (root*LF)) << 16) + 0.5*LF) / LF);}
266 #else /* FreeCalypso TCS211 reconstruction */
267 #define RATIO2(HF,LF, root, frac) \
268 { \
269 root = (UWORD32)(HF/LF); \
270 frac = (UWORD32)((((HF - (root*LF)) << 16) + 0.5*LF) / LF);}
271 #endif
272
273 #define HFTHEO(LF, root, frac, hftheo) \
274 hftheo = root*LF + ((frac*LF) >>16);
275
276 #define SUM(HF, LF, nb, ind) \
277 LF=HF=0; \
278 for(ind=0; ind<nb; ind++) \
279 { \
280 LF = LF +l1s.pw_mgr.histo[ind][0]; \
281 HF = HF +l1s.pw_mgr.histo[ind][1]; \
282 }
283
284
285 #if 0 /* FreeCalypso TCS211 reconstruction */
286 T_PWMGR_DEBUG l1_pwmgr_debug;
287 #endif
288
289
290 /* FreeCalypso: massive #if (CHIPSET == 15) chunk removed */
291
292
293 // l1ctl_pgm_clk32()
294 // convert ratio in 4.33Mhz and pgm INC_FRAC,INC_SIXTEEN.
295
296 void l1ctl_pgm_clk32(UWORD32 nb_hf, UWORD32 nb_32khz)
297 {
298 #if (CODE_VERSION != SIMULATION)
299 if (l1_config.pwr_mngt == PWR_MNGT)
300 {
301 UWORD32 inc_sixteen= 0, inc_frac=0, lf;
302
303 // REM: nb_hf is the real value of the high frequency (ex in nbr of 65Mhz clock)
304 // To compute the ratio, nb_hf must be expressed in nbr of clock 4.33 Mhz
305 // that's why nb_hf is divided by 3*l1_config.dpll
306 // RATIO2(nb_hf/(3*l1_config.dpll),nb_32khz,inc_sixteen,inc_frac);
307 // this line above is equal to the ligne below:
308 lf=(UWORD32)(3*l1_config.dpll*nb_32khz);
309 RATIO2(nb_hf,lf,inc_sixteen,inc_frac);
310
311 // integer part
312 ULDP_INCSIXTEEN_UPDATE(inc_sixteen);
313
314 // fractional part
315 ULDP_INCFRAC_UPDATE(inc_frac);
316 }
317 #endif
318 }
319
320
321 // l1ctl_gauging()
322 // Description: management of the gauging results
323 // At RESET state reset histogram and then go to INIT.
324 // At INIT state, go back to RESET on each */
325 // gauging > +- 100 ppm. If NB_INIT good gauging go to ACQUIS state.
326 // At ACQUIS state, go back to RESET on each gauging > (+- 20ppm +- 1us). If NB_ACQU good gauging */
327 // go to UPDATE state. Allow deep sleep feature.
328 // At UPDATE state, count consecutive gauging >+- 1 us.
329 // If MAX_BAD_GAUGING results go back to RESET.
330 // Otherwise re-enable deep sleep feature and reset bad results counter.
331
332 void l1ctl_gauging ( UWORD32 nb_32khz, UWORD32 nb_hf)
333 {
334 if (l1_config.pwr_mngt == PWR_MNGT)
335 {
336 enum states
337 {
338 RESET = 0,
339 INIT = 1,
340 ACQUIS = 2,
341 UPDATE = 3
342 };
343
344 static UWORD8 bad_count; // bad gauging values
345 static UWORD8 gauging_state= RESET; // RESET,INIT, ACQUIS, UPDATE
346 static UWORD8 nb_gaug; // number of gauging in ACQUIS
347 static UWORD8 idx,i; // index
348 static UWORD32 root, frac; // ratio of HF and LF average
349 UWORD32 sumLF, sumHF; // sum of HF and LF counts
350 double nbHF_theo;
351
352
353 // AFC or TEMPERATURE variation
354
355 //if ( (ABS( (WORD32)(l1s.pw_mgr.previous_afc-l1s.afc) ) > AFC_VARIATION) ||
356 // (ABS( (WORD32)(l1s.pw_mgr.previous_temp-l1s.afc) > TEMP_VARIATION) )
357 // gauging_state = RESET;
358
359 // reset state machine if not in IDLE mode
360 #if L1_GPRS
361 if ((l1a_l1s_com.l1s_en_task[NP] != TASK_ENABLED) && (l1a_l1s_com.l1s_en_task[PNP] != TASK_ENABLED))
362 gauging_state = RESET;
363 #else
364 if ((l1a_l1s_com.l1s_en_task[NP] != TASK_ENABLED) )
365 gauging_state = RESET;
366
367 #endif
368
369 switch (gauging_state)
370 {
371
372 case RESET:
373 {
374 UWORD8 i;
375
376 // Reset Histogram
377 for (i=0; i < SIZE_HIST; i++)
378 {
379 l1s.pw_mgr.histo[i][0] = 0;
380 l1s.pw_mgr.histo[i][1] = 0;
381 }
382 idx = 0;
383 l1s.pw_mgr.enough_gaug= FALSE; // forbid Deep sleep
384 gauging_state = INIT;
385 nb_gaug = NB_INIT; // counter for ACQUIS state
386 bad_count = 0; // reset count of BAD gauging
387
388 #if (TRACE_TYPE != 0)
389 l1_trace_gauging_reset();
390 #endif
391 }
392
393
394 case INIT:
395 {
396
397 // Acquire NB_INIT gauging wtw +- 100 ppm
398
399 if (l1a_l1s_com.mode != I_MODE) return;
400
401 // compute clocks ratio from measurements.
402 RATIO(nb_hf,nb_32khz,root,frac)
403
404
405 // allow [-500ppm,+100ppm] derive on 32Khz at startup.
406 #if 0 /* really old code, apparently */
407 if (
408 (root > l1s.pw_mgr.c_clk_min ||
409 (root == l1s.pw_mgr.c_clk_min &&
410 frac >= l1s.pw_mgr.c_clk_init_min) ) &&
411 (root < l1s.pw_mgr.c_clk_max ||
412 (root == l1s.pw_mgr.c_clk_max &&
413 frac <= l1s.pw_mgr.c_clk_init_max ) )
414 #elif 1 /* TCS211 reconstruction */
415 if (
416 (root == l1s.pw_mgr.c_clk_min &&
417 frac >= l1s.pw_mgr.c_clk_init_min ) ||
418 (root == l1s.pw_mgr.c_clk_max &&
419 frac <= l1s.pw_mgr.c_clk_init_max )
420 #else /* LoCosto code */
421 if (
422 ( l1s.pw_mgr.c_clk_min == l1s.pw_mgr.c_clk_max &&
423 frac >= l1s.pw_mgr.c_clk_init_min &&
424 frac <= l1s.pw_mgr.c_clk_init_max )
425 ||
426 ( l1s.pw_mgr.c_clk_min != l1s.pw_mgr.c_clk_max &&
427 ( (root == l1s.pw_mgr.c_clk_min &&
428 frac >= l1s.pw_mgr.c_clk_init_min ) ||
429 (root > l1s.pw_mgr.c_clk_min &&
430 root < l1s.pw_mgr.c_clk_max ) ||
431 (root == l1s.pw_mgr.c_clk_max &&
432 frac <= l1s.pw_mgr.c_clk_init_max ) ) )
433 #endif
434 )
435 {
436 l1s.pw_mgr.histo[idx ][0] = nb_32khz; // init histo with the number of 32kHz
437 l1s.pw_mgr.histo[idx++][1] = nb_hf; // init histo with the number of hf (13Mhz)
438
439 #if (CODE_VERSION == SIMULATION)
440 #if (TRACE_TYPE==5)
441 trace_ULPD("Gauging INIT Case ", l1s.actual_time.fn);
442 #endif
443 #endif
444
445 }
446 else
447 {
448 // out of the allowed derive -> reset
449 idx=0;
450 #if (TRACE_TYPE != 0)
451 l1_trace_gauging_reset();
452 #endif
453 }
454
455 if (idx == NB_INIT)
456 {
457 // enough measurement -> ACQUIS state
458 gauging_state = ACQUIS;
459 // compute clk ratio on count average
460 SUM(sumHF,sumLF, NB_INIT,i) // returns sumHF and sumLF
461 RATIO(sumHF,sumLF,root, frac) // returns root and frac*2E16, computed on the average
462 }
463 }
464 break;
465
466
467 case ACQUIS:
468 {
469 // Acquire NB_ACQU gauging at +-25ppm
470 // with jitter +- 1 us
471 UWORD8 n;
472
473 // from nb_32khz "measured"
474 // compute nbHF_theo
475 HFTHEO(nb_32khz,root,frac,nbHF_theo)
476
477 if ( (nb_hf >= (nbHF_theo - l1s.pw_mgr.c_delta_hf_acquis)) &&
478 (nb_hf <= (nbHF_theo + l1s.pw_mgr.c_delta_hf_acquis)) )
479 {
480 l1s.pw_mgr.histo[idx][0] = nb_32khz;
481 l1s.pw_mgr.histo[idx++][1] = nb_hf;
482 idx = idx % SIZE_HIST;
483
484 // compute clk ratio on count average
485 if(++nb_gaug >= SIZE_HIST) n=SIZE_HIST;
486 else n= nb_gaug;
487 SUM(sumHF,sumLF, n,i)
488 RATIO(sumHF,sumLF,root, frac)
489
490 #if (CODE_VERSION == SIMULATION)
491 #if (TRACE_TYPE==5)
492 trace_ULPD("Gauging ACQUIS Case ", l1s.actual_time.fn);
493 #endif
494 #endif
495
496 if ( nb_gaug == (NB_INIT+NB_ACQU)) // NB_ACQU good gauging
497 {
498 gauging_state = UPDATE; // UPDATE state
499 l1s.pw_mgr.enough_gaug = TRUE; // allow Deep sleep
500 l1ctl_pgm_clk32(sumHF,sumLF); // clocks ratio in 4.33Mhz
501 }
502 }
503 else
504 {
505 gauging_state = RESET;
506 }
507 }
508 break;
509
510 case UPDATE:
511 {
512
513 // Update gauging histogram
514 // compute nbHF theoric for ratio_avg
515 HFTHEO(nb_32khz,root,frac,nbHF_theo)
516
517 if ( (nb_hf >= (nbHF_theo-l1s.pw_mgr.c_delta_hf_update)) &&
518 (nb_hf <= (nbHF_theo+l1s.pw_mgr.c_delta_hf_update)) )
519 {
520 l1s.pw_mgr.histo[idx][0] = nb_32khz;
521 l1s.pw_mgr.histo[idx++][1] = nb_hf;
522
523 // compute clk ratio on count average
524 SUM(sumHF,sumLF, SIZE_HIST,i)
525 l1ctl_pgm_clk32(sumHF,sumLF); // clocks ratio in 4.33Mhz
526
527 l1s.pw_mgr.enough_gaug = TRUE; // allow Deep sleep
528 bad_count = 0; // reset count of BAD gauging
529
530 #if (CODE_VERSION == SIMULATION)
531 #if (TRACE_TYPE==5)
532 trace_ULPD("Gauging UPDATE Case ", l1s.actual_time.fn);
533 #endif
534 #endif
535
536 }
537 else
538 {
539 bad_count ++;
540 if (bad_count >= MAX_BAD_GAUGING) gauging_state = RESET;
541 l1s.pw_mgr.enough_gaug= FALSE; // forbid Deep sleep
542 }
543 idx = idx % SIZE_HIST;
544 }
545 break;
546 }
547 #if (TRACE_TYPE != 0) // Trace gauging
548 // save parameters in the corresponding structure
549 l1s.pw_mgr.state = gauging_state;
550 l1s.pw_mgr.lf = nb_32khz ;
551 // WARNING WARNING, this case gauging_state == UPDATE modify the algo.
552 // In case of trace the parameter root and frac are refresh.
553 // it is not the case if no trace and it seems there is mistake
554 #if 0 /* FreeCalypso TCS211 reconstruction */
555 if (gauging_state == UPDATE)
556 {
557 RATIO2(sumHF,sumLF,root,frac);
558 }
559 #endif
560 //End of Warning.
561 l1s.pw_mgr.hf = nb_hf ;
562 l1s.pw_mgr.root = root ;
563 l1s.pw_mgr.frac = frac ;
564 #endif // End Trace gauging
565 }
566 }
567
568
569 /* GAUGING_Handler() */
570 /* Description: update increment counter for 32Khz */
571 /* This interrupt function computes the ratio between */
572 /* HF/32Khz gauging counters and program ULPD increment */
573 /* values. */
574
575 void GAUGING_Handler(void)
576 {
577 #if (CODE_VERSION != SIMULATION)
578 if (l1_config.pwr_mngt == PWR_MNGT)
579 {
580 UWORD32 nb_32khz, nb_hf;
581
582 // Gauging task is ended
583 l1s.pw_mgr.gauging_task = INACTIVE;
584 #if (CHIPSET == 12) || (CHIPSET == 15)
585 F_INTH_DISABLE_ONE_IT(C_INTH_ULPD_GAUGING_IT); // Mask ULPD GAUGING int.
586 #else
587 INTH_DISABLEONEIT(IQ_ULPD_GAUGING); // Mask ULPD GAUGING int.
588 #endif
589
590 // Number of 32 Khz clock at the end of the gauging
591 nb_32khz = ((*( UWORD16 *)ULDP_COUNTER_32_MSB_REG) * 65536) +
592 (*( UWORD16 *)ULDP_COUNTER_32_LSB_REG);
593
594 // Number of high frequency clock at the end of the gauging
595 // Convert it in nbr of 13 Mhz clocks (5*13=65Mhz)
596 nb_hf = ( ((*( UWORD16 *)ULDP_COUNTER_HI_FREQ_MSB_REG) * 65536) +
597 (*( UWORD16 *)ULDP_COUNTER_HI_FREQ_LSB_REG) ); // Divide by PLL ratio
598
599 l1ctl_gauging(nb_32khz, nb_hf);
600 }
601 #else //Simulation part
602
603 // Gauging task is ended
604 l1s.pw_mgr.gauging_task = INACTIVE;
605
606 l1ctl_gauging(DEFAULT_32KHZ_VALUE,DEFAULT_HFMHZ_VALUE);
607 #endif
608 }
609
610
611 // l1s_get_HWTimers_ticks()
612 // Description:
613 // evaluate the loading of the HW Timers for dep sleep
614 // BIG SLEEP: timers CLK may be stopped (user dependant)
615 // DEEP SLEEP:timers CLK and WTCHDOG CLK are stopped
616 // CLKS are enabled after VTCX0+SLICER+13MHZ
617 // setup time
618
619 WORD32 l1s_get_HWTimers_ticks(void)
620 {
621 #if (CODE_VERSION != SIMULATION)
622 WORD32 timer1,timer2,watchdog,HWTimer;
623 #if (CHIPSET == 12) || (CHIPSET == 15)
624 WORD32 watchdog_sec;
625 #endif
626 UWORD16 cntlreg;
627 UWORD16 modereg;
628 WORD32 old = 0;
629
630 // read Hercules Timers & Watchdog
631 //=================================================
632 // Tint = Tclk * (LOAD_TIM+1) * 2^(PTV+1)
633 // Tclk = 1.2308us for Fclk=13Mhz
634 // PTV = X (pre-scaler field)
635 //-------------------------------------------------
636 timer1 = timer2 = watchdog = HWTimer = -1;
637 #if (CHIPSET == 12) || (CHIPSET == 15)
638 watchdog_sec = -1;
639 #endif
640
641 cntlreg = Dtimer1_Get_cntlreg(); // AND 0x1F
642 if ( (cntlreg & D_TIMER_RUN) == D_TIMER_RUN)
643 {
644 #if 0 /* match TCS211 object */
645 cntlreg = cntlreg&0x1F;
646 #endif
647 cntlreg >>= 2; // take PTV
648 cntlreg = 1 << (cntlreg+1);
649 timer1 = (WORD32) ( ((Dtimer1_ReadValue()+1) * cntlreg * 0.0012308) / 4.615 );
650 if (timer1 <= MIN_SLEEP_TIME) return(0);
651 old = Dtimer1_ReadValue();
652 HWTimer = timer1;
653 }
654
655 cntlreg = Dtimer2_Get_cntlreg();
656 if ( (cntlreg & D_TIMER_RUN) == D_TIMER_RUN)
657 {
658 #if 0 /* match TCS211 object */
659 cntlreg = cntlreg&0x1F;
660 #endif
661 cntlreg >>= 2; // take PTV
662 cntlreg = 1 << (cntlreg+1);
663 timer2 = (WORD32) ( ((Dtimer2_ReadValue()+1) * cntlreg * 0.0012308) / 4.615 );
664 if (timer2 <= MIN_SLEEP_TIME) return(0);
665 if (HWTimer == -1) HWTimer = timer2;
666 else MIN(HWTimer,timer2)
667 }
668
669 cntlreg = TIMER_Read(0); // AND 0x0f80
670 modereg = TIMER_Read(2);
671
672 if ( (cntlreg & TIMER_ST) || (modereg & TIMER_WDOG))
673 {
674 // in watchdog mode PTV is forced to 7
675 if ( modereg & TIMER_WDOG )
676 cntlreg |= TIMER_PTV;
677
678 cntlreg = (cntlreg & TIMER_PTV) >> 9; // take PTV
679 cntlreg = 1 << (cntlreg+1);
680 watchdog = (WORD32) ( ((TIMER_ReadValue()+1) * cntlreg * 0.001078) / 4.615 );
681 if (watchdog <= MIN_SLEEP_TIME) return(0);
682 if (HWTimer == -1) HWTimer = watchdog;
683 else MIN(HWTimer,watchdog)
684 }
685
686 #if (CHIPSET == 12) || (CHIPSET == 15)
687 /*
688 * Secure Watchdog Timer management
689 */
690 cntlreg = TIMER_SEC_Read(0); // AND 0x0f80
691 modereg = TIMER_SEC_Read(2);
692 if ( (cntlreg & TIMER_ST) || (modereg & TIMER_WDOG))
693 {
694 // in watchdog mode PTV is forced to 7
695 if ( modereg & TIMER_WDOG )
696 cntlreg |= TIMER_PTV;
697
698 cntlreg = (cntlreg & TIMER_PTV) >> 9; // take PTV
699 cntlreg = 1 << (cntlreg+1);
700 watchdog_sec = (WORD32) ( ((TIMER_SEC_ReadValue()+1) * cntlreg * 0.001078) / 4.615 );
701 if (watchdog_sec <= MIN_SLEEP_TIME) return(0);
702 if (HWTimer == -1) HWTimer = watchdog_sec;
703 else MIN(HWTimer,watchdog_sec)
704 }
705
706 #endif
707
708 return (HWTimer);
709 #else // simulation part
710 return (-1); // no HW timer in simulation
711 #endif
712 }
713
714 #if (GSM_IDLE_RAM != 0) // Compile only if GSM_IDLE_RAM enabled
715
716 void l1s_adapt_traffic_controller(void)
717 {
718 BOOL l1s_extram;
719 UWORD8 nb_bitmap;
720 T_L1S_GSM_IDLE_INTRAM * gsm_idle_ram_ctl;
721
722 gsm_idle_ram_ctl = &(l1s.gsm_idle_ram_ctl);
723
724 l1s_extram = FALSE;
725
726 for(nb_bitmap=0; ((nb_bitmap < SIZE_TAB_L1S_MONITOR) && (l1s_extram == FALSE)); nb_bitmap++)
727 {
728 if (nb_bitmap == 1)
729 {
730 l1s_extram |= (((INT_RAM_GSM_IDLE_L1S_PROCESSES1 ^ gsm_idle_ram_ctl->task_bitmap_idle_ram[nb_bitmap]) & gsm_idle_ram_ctl->task_bitmap_idle_ram[nb_bitmap]) != 0);
731 }else
732 {
733 l1s_extram |= (gsm_idle_ram_ctl->task_bitmap_idle_ram[nb_bitmap] != 0);
734 }
735 }
736
737 if ((l1s_extram != FALSE) && (!READ_TRAFFIC_CONT_STATE))
738 {
739 CSMI_TrafficControllerOn();
740 #if (TRACE_TYPE==1) || (TRACE_TYPE==4)
741 {
742 l1s_trace_mftab();
743 }
744 #endif
745 }
746 }
747 #endif
748
749 UWORD32 last_wakeup = 0;
750 UWORD8 wakeup_type; // Type of the interrupt
751 UWORD8 why_big_sleep; // Type of the big sleep
752
753 extern UWORD16 int_id;
754
755 // l1s_sleep_manager()
756 // Description:
757 // evaluate the loading of the system
758 // - SIM, UART, LCD ....
759 // - Nucleus tasks, Hisrs, timers
760 // - Timer1, Timer2, Watchdog
761 // program Big or Deep sleep
762
763 void l1s_sleep_manager()
764 {
765 //UWORD8 temp=0; OMAPS00090550
766
767 UWORD16 temp_clear_intr;
768
769 // fn when l1s_sleep_manager function is called
770 #if (CODE_VERSION != SIMULATION)
771 UWORD32 sleep_time = l1s.actual_time.fn_mod42432;
772 #else
773 UWORD32 sleep_time = l1s.actual_time.fn;
774 #endif
775
776 if (l1_config.pwr_mngt == PWR_MNGT)
777 {
778 // Power management is enabled
779 WORD32 min_time, HWtimer,wake_up_time,min_time_gauging;
780 WORD32 afc_fix;
781 static UWORD32 previous_sleep = CLOCK_STOP;
782 #if (W_A_CALYPSO_PLUS_SPR_19599 == 1)
783 BOOL extended_page_mode_state = 0; //Store state of extended page mode
784 #endif
785 WORD32 time_from_last_wakeup=0;
786 UWORD32 sleep_mode;
787
788 #if (OP_BT == 1)
789 WORD32 hci_ll_status;
790 #endif
791
792 // init for trace and debug
793 why_big_sleep = BIG_SLEEP_DUE_TO_UNDEFINED;
794 wakeup_type = WAKEUP_FOR_UNDEFINED;
795
796 time_from_last_wakeup = (sleep_time - last_wakeup + 42432) % 42432;
797
798 //=================================================
799 // check System (SIM, UART, LDC ..... )
800 //=================================================
801 sleep_mode = Cust_check_system();
802
803 if (sleep_mode == DO_NOT_SLEEP)
804 return;
805
806 #if (CODE_VERSION != SIMULATION)
807 //=================================================
808 // Protect System structures
809 // must be called BEFORE INT_DisableIRQ() while
810 // Nucleus does not restore IRQ/FIQ bits !!!!
811 //=================================================
812 OS_system_protect();
813 //=================================================
814 // Disable IRQ
815 //=================================================
816 INT_DisableIRQ();
817 #endif // NOT SIMULATION
818
819 //=================================================
820 // check OS loading
821 //=================================================
822 min_time = OS_get_inactivity_ticks();
823
824 //=================================================
825 // check HW Timers loading
826 //=================================================
827 HWtimer= l1s_get_HWTimers_ticks();
828
829 //=================================================
830 // check next gauging task for Packet Idle
831 //=================================================
832 #if L1_GPRS
833 min_time_gauging = l1s_get_next_gauging_in_Packet_Idle();
834 #else
835 min_time_gauging = -1; // not used
836 #endif
837
838 #if (OP_BT == 1)
839 hci_ll_status = hci_ll_ok_for_sleep();
840 #endif
841 // check if immediate activity planned
842 // 0 means immediate activity
843 // in case big sleep is choosen (sleep mode == FRAME_STOP) because of UART or SIM,
844 // return and wait end of this activity (few TDMA frames) then check on next TDMA frames
845 // if MS can go in deep sleep
846 if ( !min_time
847 || !HWtimer
848 || !min_time_gauging
849 || (sleep_mode != CLOCK_STOP)
850 #if (OP_BT == 1)
851 || !hci_ll_status
852 #endif
853 )
854 {
855
856
857 #if (CODE_VERSION != SIMULATION)
858 OS_system_Unprotect();
859 // free System structure
860 // Enable all IRQ
861 INT_EnableIRQ();
862 // Wake up UART
863
864 SER_WakeUpUarts(); // Wake up Uarts
865
866 #endif
867 return;
868 }
869 //=================================================
870 // Select sleep duration ....
871 //=================================================
872 // remember: -1 means no activity planned
873 //l1a_l1s_com.time_to_next_l1s_task is UW32, min_time is W32. Max value of l1a_l1s_com.time_to_next_l1s_task will be 2p31
874 //and ,min_time max value will be 2p30. If min_time > l1a_l1s_com.time_to_next_l1s_task,
875 //means MSB of l1a_l1s_com.time_to_next_l1s_task is zero. so, we can use- uw32_store_next_time & 0x7FFFFFFF
876
877 if (min_time == -1) min_time = l1a_l1s_com.time_to_next_l1s_task;
878 else MIN(min_time, l1a_l1s_com.time_to_next_l1s_task)
879 if (HWtimer != -1) MIN(min_time, HWtimer)
880 if (min_time_gauging != -1) MIN(min_time, min_time_gauging)
881
882 #if (TRACE_TYPE !=0 ) && (TRACE_TYPE != 2) && (TRACE_TYPE != 3)
883 // to trace the Wake up source
884 // depending of min_time choose the wakeup_type
885 wakeup_type = WAKEUP_FOR_OS_TASK;
886 if (min_time == l1a_l1s_com.time_to_next_l1s_task) wakeup_type = WAKEUP_FOR_L1_TASK;
887 if (min_time == HWtimer) wakeup_type = WAKEUP_FOR_HW_TIMER_TASK;
888 if (min_time == min_time_gauging) wakeup_type = WAKEUP_FOR_GAUGING_TASK;
889 #endif
890
891 //=================================================
892 // Choose DEEP or BIG SLEEP
893 //=================================================
894 if ( ((l1s.pw_mgr.mode_authorized == DEEP_SLEEP) && (sleep_mode == CLOCK_STOP)) ||
895 ((l1s.pw_mgr.mode_authorized == ALL_SLEEP) && (sleep_mode == CLOCK_STOP)) )
896 {
897 // Check now gauging histogramme or if in inactive period of cell selection
898 #if (W_A_DSP_IDLE3 == 1) && (CODE_VERSION!=SIMULATION)
899 if (((l1s.pw_mgr.enough_gaug == TRUE) || (l1a_l1s_com.mode == CS_MODE0)) &&
900 ( l1s_dsp_com.dsp_ndb_ptr->d_dsp_state == C_DSP_IDLE3))
901 #else
902 #if (CHIPSET == 12) || (CHIPSET == 15)
903 if (((l1s.pw_mgr.enough_gaug == TRUE) || (l1a_l1s_com.mode == CS_MODE0)) &&
904 !CLKM_READ_nIDLE3)
905 #else
906 if ((l1s.pw_mgr.enough_gaug == TRUE) || (l1a_l1s_com.mode == CS_MODE0))
907 #endif
908 #endif
909 l1s.pw_mgr.sleep_performed = CLOCK_STOP;
910 else
911 {
912 // BIG SLEEP is chosen : check the reason
913 l1s.pw_mgr.sleep_performed = FRAME_STOP;
914 if (l1s.pw_mgr.enough_gaug != TRUE)
915 why_big_sleep = BIG_SLEEP_DUE_TO_GAUGING;
916 else
917 why_big_sleep = BIG_SLEEP_DUE_TO_DSP_TRACES;
918 }
919 }
920 if (l1s.pw_mgr.mode_authorized == BIG_SLEEP)
921 why_big_sleep = BIG_SLEEP_DUE_TO_SLEEP_MODE;
922
923 if ( ((l1s.pw_mgr.mode_authorized == BIG_SLEEP) && (sleep_mode >= FRAME_STOP)) ||
924 ((l1s.pw_mgr.mode_authorized >= DEEP_SLEEP) && (sleep_mode == FRAME_STOP)) )
925 l1s.pw_mgr.sleep_performed = FRAME_STOP;
926
927
928 if ((previous_sleep == CLOCK_STOP) && (time_from_last_wakeup < 7))
929 {
930 #if (CODE_VERSION != SIMULATION)
931 OS_system_Unprotect(); // free System structure
932 INT_EnableIRQ(); // Enable all IRQ
933
934 SER_WakeUpUarts(); // Wake up Uarts
935
936 #endif // NOT SIMULATION
937 return;
938 }
939
940 // update previous sleep
941 previous_sleep = l1s.pw_mgr.sleep_performed;
942
943
944 #if (CODE_VERSION != SIMULATION)
945
946 #if (CHIPSET == 12) || (CHIPSET == 15)
947 F_INTH_DISABLE_ONE_IT(C_INTH_FRAME_IT); // mask Frame int.
948 #else
949 INTH_DISABLEONEIT(IQ_FRAME); // mask Frame int.
950 #endif
951 #endif
952
953 //=====================================================
954 // if CLOCK_STOP : stop RF, TPU, asleep Omega, DPLL, SPI
955 // if FRAME_STOP : asleep Omega, SPI
956 //=====================================================
957 #if (CODE_VERSION != SIMULATION)
958 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP )
959 {
960 // ==== STop RF and TPU..... ===================
961
962 //L1_trace_string("Proceeding to Deep Sleep\n");
963
964
965 l1dmacro_RF_sleep();
966
967 // (*(volatile UWORD16 *)l1s_tpu_com.reg_cmd) =TPU_CTRL_RESET |
968 // TSP_CTRL_RESET |TPU_CTRL_CLK_EN;
969 // (*(volatile UWORD16 *)l1s_tpu_com.reg_cmd) =0;
970
971 //===== SET default value for gauging =========
972 // If we have come in here during the inactive period of cell
973 // selection, then load the ULPD timers with default values
974 // (used when the MS lost the network: in this case the deep sleep may be used)
975 if (l1a_l1s_com.mode == CS_MODE0)
976 {
977 l1ctl_pgm_clk32(DEFAULT_HFMHZ_VALUE, DEFAULT_32KHZ_VALUE);
978 }
979 }
980
981
982 //==============================================
983 // disable DPLL (do not provide clk to DSP & RIF (RIF))
984 //==============================================
985 #if ((CHIPSET ==4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15))
986 // disable DPLL (do not provide clk to DSP & RIF (Bridge))
987 ( * (volatile SYS_UWORD16 *) CLKM_CNTL_CLK) |= CLKM_DPLL_DIS | CLKM_BRIDGE_DIS;
988 #endif
989
990 //==============================================
991 // if CLOCK_STOP or FRAME-STOP : Asleep OMEGA (ABB)
992 //==============================================
993 afc_fix = ABB_sleep(l1s.pw_mgr.sleep_performed, l1s.afc);
994
995 #if (OP_BT == 1)
996 hci_ll_go_to_sleep();
997 #endif
998 //=================================================
999 // STop SPI .....
1000 //=================================================
1001
1002 *((volatile UWORD16 *)MEM_SPI)&=0xFFFE; // SPI CLK DISABLED
1003 #endif // NOT SIMULATION
1004
1005
1006 //=================================================
1007 // CQ19599: For Calypso+ chipset, extended page mode
1008 // shall be disabled before entering deep sleep and
1009 // restored at wake up
1010 //=================================================
1011 #if (W_A_CALYPSO_PLUS_SPR_19599 == 1)
1012 extended_page_mode_state = (BOOL) f_memif_extended_page_mode_read_bit();
1013 f_memif_extended_page_mode_disable();
1014 #endif
1015
1016 //=================================================
1017 // Init the timer :
1018 //
1019 // a margin of 4 frames (>MIN_SLEEP_TIME) is taken
1020 // when evaluating system loading, because 1 frame
1021 // is lost for wakeup only, and because sleep
1022 // duration less than 1 frame is not worth ....
1023 //
1024 // 1 2 3 4 5 6 7 8
1025 // SLEEP_CTRL SLEEP WAKEUP TASK (RF,Timer, ...)
1026 //
1027 //=================================================
1028 //ULPD Timer can be loaded up to MAX_GSM_TIMER (possible in CS_MODE0)
1029 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP )
1030 {
1031 // DEEP SLEEP -> need time to setup afc and rf
1032 wake_up_time = min_time - l1_config.params.setup_afc_and_rf;
1033 }
1034 else
1035 // BIG SLEEP
1036 wake_up_time = min_time - 1;
1037
1038
1039
1040 #if (CODE_VERSION != SIMULATION)
1041 if ( wake_up_time >= MAX_GSM_TIMER)
1042 ULDP_TIMER_INIT(MAX_GSM_TIMER);
1043 else
1044 ULDP_TIMER_INIT(wake_up_time);
1045
1046 ULDP_TIMER_LD; // Load the timer
1047
1048 // BUG3060. Clear pending IQ_TGSM from ULPD. This could happen in case ULPD was frozen
1049 // with zero into its GSM counter. In that case, the interrupt is still pending
1050 // and if it is not cleared, it wakes the board up just after switching the clock.
1051 // Clear it into the ULPD...
1052 // The ULDP_GSM_TIMER_IT_REG is a read only register and is cleared on
1053 //reading the register.
1054 temp_clear_intr =(* (volatile UWORD16 *) ULDP_GSM_TIMER_IT_REG) & ULPD_IT_TIMER_GSM;
1055 // ... and next into the INTH. (must be done in this order
1056
1057 #if (CHIPSET == 12) || (CHIPSET == 15)
1058 F_INTH_RESET_ONE_IT(C_INTH_TGSM_IT);
1059 F_INTH_ENABLE_ONE_IT(C_INTH_TGSM_IT);
1060 #else
1061 INTH_RESETONEIT(IQ_TGSM); // clear TDMA IRQ
1062 INTH_ENABLEONEIT(IQ_TGSM); // Unmask ULPD GSM int.
1063 #endif
1064
1065 #if (GSM_IDLE_RAM != 0)
1066 if (READ_TRAFFIC_CONT_STATE)
1067 {
1068 CSMI_TrafficControllerOff();
1069 }
1070 #endif
1071
1072 ULDP_TIMER_START; // start count down
1073
1074
1075 #if (GSM_IDLE_RAM_DEBUG == 1)
1076 (*( volatile unsigned short* )(0xFFFE4802)) &= ~ (1 << 2); // GPIO-2=0
1077 #endif
1078
1079 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP )
1080 // DEEP SLEEP
1081 {
1082 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1)
1083 // specific sleep for WCP
1084 arm7_deep_sleep();
1085 #else // NO OP_WCP
1086 #if (W_A_CALYPSO_BUG_01435 == 1)
1087 f_arm_sleep_cmd(DEEP_SLEEP);
1088 #else
1089 *((volatile UWORD16 *)CLKM_ARM_CLK) &= ~(CLKM_DEEP_SLEEP); // set deep sleep mode
1090 #endif
1091 #endif // OP_WCP
1092 }
1093 else
1094 {
1095 // BIG SLEEP / l1s.pw_mgr.sleep_performed == FRAME_STOP
1096
1097 //==========================================================
1098 //Shut down PERIPHERALS clocks UWIRE and ARMIO if authorized
1099 //==========================================================
1100
1101 UWORD16 clocks_stopped; //OMAPS90550- new
1102 clocks_stopped = (l1s.pw_mgr.clocks & l1s.pw_mgr.modules_status);
1103 if((clocks_stopped & ARMIO_CLK_CUT) == ARMIO_CLK_CUT)
1104 *((volatile UWORD16 *)ARMIO_CNTL_REG) &= ~(ARMIO_CLOCKEN);
1105 if((clocks_stopped & UWIRE_CLK_CUT) == UWIRE_CLK_CUT)
1106 *((volatile UWORD16 *)(MEM_UWIRE + 0x8)) &= ~(0x0001);
1107
1108 #if (W_A_CALYPSO_BUG_01435 == 1)
1109 f_arm_sleep_cmd(BIG_SLEEP);
1110 #else
1111
1112 *((volatile UWORD16 *)CLKM_ARM_CLK) &= ~(CLKM_MCLK_EN); // set big sleep mode
1113 #endif
1114 }
1115 #else // Simulation part
1116 l1s.pw_mgr.sleep_duration = wake_up_time;
1117 hw.deep_sleep_en = 1;
1118 status = NU_Suspend_Task(&L1S_task);
1119 // check status value...
1120 if (status)
1121 {
1122 #if (TRACE_TYPE==5)
1123 sprintf(errormsg,"Error somewhere in the L1S application to suspend : deep sleep\n");
1124 log_sim_error(ERR);
1125 #endif
1126 EXIT;
1127 }
1128 #endif // SIMULATION
1129
1130 //=================================================
1131 // Wake-up procedure
1132 //=================================================
1133 // Restore L1 data base, Nucleus, HW Timers ....
1134 //=================================================
1135
1136 #if (GSM_IDLE_RAM_DEBUG == 1)
1137 (*( volatile unsigned short* )(0xFFFE4802)) |= (1 << 2); // GPIO-2=1
1138 #endif
1139
1140
1141 l1s_wakeup();
1142
1143 last_wakeup = l1s.actual_time.fn_mod42432;
1144
1145 if (last_wakeup == sleep_time)
1146 // sleep duration == 0 -> wakeup in the same frame as sleep
1147 wakeup_type = WAKEUP_ASYNCHRONOUS_SLEEP_DURATION_0;
1148
1149 #if (GSM_IDLE_RAM != 0)
1150 // Update counters with sleep duration -> will be used case expiration in next wake up phase before traffic controller is enabled by msg sending
1151 gsm_idle_ram_ctl->os_load -= (l1s.pw_mgr.sleep_duration);
1152 gsm_idle_ram_ctl->hw_timer -= (l1s.pw_mgr.sleep_duration);
1153
1154 if (l1s.pw_mgr.wakeup_type != WAKEUP_FOR_L1_TASK)
1155 {
1156 if (!READ_TRAFFIC_CONT_STATE)
1157 {
1158 CSMI_TrafficControllerOn();
1159 }
1160 }
1161 #endif
1162 //=================================================
1163 //if CLOCK_STOP : restart TPU and RF....
1164 //=================================================
1165 #if (CODE_VERSION != SIMULATION)
1166 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP )
1167 {
1168 // (*(volatile UWORD16 *)l1s_tpu_com.reg_cmd) = TPU_CTRL_CLK_EN;
1169 UWORD8 local_sleep_status;
1170
1171 l1dmacro_RF_wakeup();
1172
1173 }
1174
1175 #if ((CHIPSET ==4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
1176 // enable DPLL (provide clk to DSP & RIF(Bridge) in small/big sleep)
1177 // On CALYPSO, BRIDGE clock can be cut according to the ARM sleep mode even during DMA transfer
1178 ( * (volatile SYS_UWORD16 *) CLKM_CNTL_CLK) &= ~(CLKM_DPLL_DIS | CLKM_BRIDGE_DIS);
1179 #elif (CHIPSET == 12)
1180 // Nothing to be done because if DSP wants clock, it will exit from IDLE3 mode, which wakes up the DPLL
1181 #elif (CHIPSET == 15)
1182 ( * (volatile SYS_UWORD16 *) CLKM_CNTL_CLK) &= ~(CLKM_DPLL_DIS);
1183 #endif
1184
1185 //=================================================
1186 //if CLOCK_STOP or FRAME-STOP : ReStart SPI
1187 //=================================================
1188 *((volatile UWORD16 *)MEM_SPI)|=0x0001; // SPI CLK ENABLED
1189
1190 //=================================================
1191 // Wake up ABB
1192 //=================================================
1193 ABB_wakeup(l1s.pw_mgr.sleep_performed, l1s.afc);
1194
1195 #if (OP_BT == 1)
1196 hci_ll_wake_up();
1197 #endif
1198 #endif //CODE VERSION
1199
1200 //=================================================
1201 // CQ19599: For Calypso+ chipset, restore the extended
1202 // page mode if it was enabled before entering in sleep
1203 //=================================================
1204 #if (W_A_CALYPSO_PLUS_SPR_19599 == 1)
1205 if ( extended_page_mode_state != 0 )
1206 f_memif_extended_page_mode_enable();
1207 #endif
1208
1209 #if (OP_L1_STANDALONE == 0)
1210 /*GC_Wakeup(); OMAPS00134004*/
1211 #endif
1212
1213 #if (CODE_VERSION != SIMULATION)
1214 //=================================================
1215 // enable IRQ
1216 //=================================================
1217 OS_system_Unprotect();
1218 #endif
1219
1220 #if (TRACE_TYPE != 0)
1221 if (l1a_l1s_com.mode != CS_MODE0) // in this mode the trace prevent from going to deep sleep due to UART activity
1222 {
1223 #if (GSM_IDLE_RAM == 0)
1224 l1_trace_sleep(sleep_time, l1s.actual_time.fn_mod42432, l1s.pw_mgr.sleep_performed, wakeup_type, why_big_sleep);
1225 #else
1226 l1_trace_sleep_intram(sleep_time, l1s.actual_time.fn_mod42432, l1s.pw_mgr.sleep_performed, wakeup_type, why_big_sleep);
1227 #if (TRACE_TYPE==1) || (TRACE_TYPE==4)
1228 l1s_trace_mftab();
1229 #endif
1230 #endif
1231 }
1232 #endif
1233
1234 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4)
1235 trace_info.sleep_performed = TRUE;
1236 #endif
1237
1238 #if (CODE_VERSION != SIMULATION)
1239
1240 //=================================================
1241 // enable IRQ
1242 //=================================================
1243 INT_EnableIRQ();
1244
1245 //=================================================
1246 // Be careful:in case of asynchronous wake-up after sleep
1247 // an IT_TDMA may be unmasked and executed just after OS_system_Unprotect().
1248 // As we already are inside an hisr(), it implies the execution of an another hisr().
1249 // In order to avoid issues with the execution of an hisr() inside the hisr()
1250 // do not add code here after !!!
1251 // if possible respect this rule !
1252 //=================================================
1253
1254 //=================================================
1255 // wake-up UARTs
1256 //this function must be call after the UART interrupt,
1257 //it means after the function INT_EnableIRQ()
1258 //=================================================
1259 {
1260 #if (GSM_IDLE_RAM != 0)
1261 // Traffic controller has to be enabled before calling SER_WakeUpUarts
1262 // as this function can access the external RAM.
1263 // Reset the flag that will indicates if an interrup will put the traffic
1264 // controller ON during that time.
1265 l1s.gsm_idle_ram_ctl.trff_ctrl_enable_cause_int = FALSE;
1266 if (!READ_TRAFFIC_CONT_STATE)
1267 {
1268 flag_traffic_controller_state = 1;
1269 CSMI_TrafficControllerOn();
1270 }
1271 #endif
1272
1273
1274 SER_WakeUpUarts(); // Wake up Uarts
1275
1276
1277 #if (GSM_IDLE_RAM != 0)
1278 // The traffic controller state shall be restored as it was before
1279 // calling SER_WakeUpUarts. Do not disable it if an interrup occured
1280 // in between and activated the traffic controller.
1281 if ((flag_traffic_controller_state == 1) && (l1s.gsm_idle_ram_ctl.trff_ctrl_enable_cause_int == FALSE))
1282 {
1283 CSMI_TrafficControllerOff();
1284 }
1285 flag_traffic_controller_state = 0;
1286 #endif
1287 }
1288 #endif // NOT SIMULATION
1289 }
1290 }
1291
1292 // l1s_wakeup() */
1293 // Description: wake-up of the MCU from GSM Timer it OR unscheduled wake-up
1294 // This function read the TPU timer and fix the :
1295 // - system clock
1296 // - Nucleus timers
1297 // - L1 frame counter
1298 // - L1 next task counter
1299 // - Hardware timers
1300
1301 void l1s_wakeup(void)
1302 {
1303 #if (CODE_VERSION != SIMULATION)
1304 if (l1_config.pwr_mngt == PWR_MNGT)
1305 {
1306 // Restore interrupts ....
1307
1308 #if (CHIPSET == 12) || (CHIPSET == 15)
1309 // mask TGSM int.
1310 F_INTH_DISABLE_ONE_IT(C_INTH_TGSM_IT);
1311 #else
1312 INTH_DISABLEONEIT(IQ_TGSM); // mask TGSM int.
1313 #endif
1314
1315 #if (CHIPSET == 12) || (CHIPSET == 15)
1316 int_id = ((* (SYS_UWORD16 *) C_INTH_B_IRQ_REG) & C_INTH_SRC_NUM);// For debug: Save IRQ that causes the waking up
1317 if ( int_id >= 256 )
1318 int_id = ((* (SYS_UWORD16 *) C_INTH_B_FIQ_REG) & C_INTH_SRC_NUM)+100;
1319 #else
1320 int_id = ((* (SYS_UWORD16 *) INTH_B_IRQ_REG) & INTH_SRC_NUM);// For debug: Save IRQ that causes the waking up
1321 if ( int_id >= 256 )
1322 int_id = ((* (SYS_UWORD16 *) INTH_B_FIQ_REG) & INTH_SRC_NUM)+100;
1323 #endif
1324
1325 // clear pending IQ_FRAME it and unmask it
1326 #if (CHIPSET == 12) || (CHIPSET == 15)
1327 F_INTH_RESET_ONE_IT(C_INTH_FRAME_IT);
1328 F_INTH_ENABLE_ONE_IT(C_INTH_FRAME_IT); // Unmask FRAME int.
1329 #else
1330 INTH_RESETONEIT(IQ_FRAME); // clear TDMA IRQ
1331 INTH_ENABLEONEIT(IQ_FRAME); // Unmask FRAME int.
1332 #endif
1333
1334 #if (CHIPSET == 8)
1335 // if deep sleep
1336 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP )
1337 {
1338 UWORD8 i;
1339
1340 // Loop with check whether DPLL is locked: 100 us max.
1341 for (i=0;i<16;i++)
1342 {
1343 if (DPLL_READ_DPLL_LOCK)
1344 break;
1345 }
1346 wait_ARM_cycles(convert_nanosec_to_cycles(50000)); // 50us
1347
1348 // Enable DPLL
1349 //--------------------------------------------------
1350 DPLL_SET_PLL_ENABLE;
1351
1352 // Loop with check whether DPLL is locked: 100 us max.
1353 for (i=0;i<16;i++)
1354 {
1355 if (DPLL_READ_DPLL_LOCK)
1356 break;
1357 }
1358 wait_ARM_cycles(convert_nanosec_to_cycles(50000)); // 50us
1359 } // if deep sleep
1360
1361 #endif // CHIPSET == 8
1362
1363 //=================================================
1364 //Restart PERIPHERALS clocks if necessary after a big sleep period
1365 // WARNING: restart other clocks modules!!!
1366 //=================================================
1367
1368
1369 #if(CHIPSET == 15)
1370 if(l1s.pw_mgr.sleep_performed == FRAME_STOP )
1371 {
1372
1373 //ABB_Wakeup_BS(); //Not Used
1374 //DBB_Wakeup_BS(); //Not Used
1375 }
1376 #else
1377 // if big sleep
1378 if ( l1s.pw_mgr.sleep_performed == FRAME_STOP )
1379 {
1380
1381 UWORD16 clocks_stopped;
1382 clocks_stopped = (l1s.pw_mgr.clocks & l1s.pw_mgr.modules_status);
1383 if((clocks_stopped & ARMIO_CLK_CUT) == ARMIO_CLK_CUT)
1384 *((volatile UWORD16 *)ARMIO_CNTL_REG) |= ARMIO_CLOCKEN;
1385 if((clocks_stopped & UWIRE_CLK_CUT) == UWIRE_CLK_CUT)
1386 *((volatile UWORD16 *)(MEM_UWIRE + 0x8)) |= 0x0001;
1387
1388 }
1389 #endif
1390
1391
1392 /***************************************************/
1393 /* Compute effective sleeping time .... */
1394 /* */
1395 /* sleep duration is */
1396 /* - TIMER_INIT */
1397 /* - or TIMER_INIT - TIMER_VALUE */
1398 /* */
1399 /* "frame_adjust" = TRUE for unschedules wake-up */
1400 /* FALSE for scheduled wake-up */
1401 /***************************************************/
1402 l1s.pw_mgr.frame_adjust = l1s_compute_wakeup_ticks();
1403
1404 #if (TRACE_TYPE !=0 ) && (TRACE_TYPE != 2) && (TRACE_TYPE != 3)
1405 if ((l1s.pw_mgr.frame_adjust == TRUE))
1406 wakeup_type = WAKEUP_BY_ASYNC_INTERRUPT;
1407 #endif
1408
1409
1410 /* Fix Frame */
1411
1412 l1s_recover_Frame();
1413
1414
1415 /* Fix Hardware Timers */
1416 /* */
1417 /* GSM 1.0 : ntd - timer clock not cut */
1418 /* */
1419 /* GSM 1.5 : deep sleep - need to fix timers */
1420
1421 if (l1s.pw_mgr.sleep_performed == CLOCK_STOP)
1422 l1s_recover_HWTimers();
1423
1424
1425 /* Fix Os */
1426
1427 if (Cust_recover_Os()) l1s.pw_mgr.Os_ticks_required = TRUE;
1428 }
1429 #else // SIMULATION part
1430 // update L1 timers (FN,...)
1431 l1s_recover_Frame();
1432 #endif
1433 }
1434
1435
1436
1437 /* l1s_wakeup_adjust() */
1438 /* Description: 1 frame adjust a fter unscheduled wake-up */
1439 /* This function fix the : */
1440 /* - system clock */
1441 /* - Nucleus timers */
1442 /* - L1 frame counter */
1443 /* - L1 next task counter */
1444 /* - Hardware timers */
1445
1446
1447 void l1s_wakeup_adjust ()
1448 {
1449 #if (CODE_VERSION != SIMULATION)
1450 if (l1_config.pwr_mngt == PWR_MNGT)
1451 {
1452
1453 UWORD32 previous_sleep_time;
1454
1455 /***************************************************/
1456 // Freeze GSM Timer .... */
1457 /***************************************************/
1458 ULDP_TIMER_FREEZE;
1459
1460 /***************************************************/
1461 // Compute effective sleeping time ....
1462 //
1463 // compute sleep duration
1464 // - TIMER_INIT
1465 // - or TIMER_INIT - TIMER_VALUE
1466 /***************************************************/
1467 // save sleep duration that was computed at "unscheduled wakeup"
1468 previous_sleep_time = l1s.pw_mgr.sleep_duration;
1469
1470 l1s_compute_wakeup_ticks();
1471
1472 // reset flag for adjustment request ....
1473 l1s.pw_mgr.frame_adjust = FALSE;
1474
1475 // fix sleep duration
1476 // => compute difference with duration computed at
1477 // "unscheduled wakeup"
1478 l1s.pw_mgr.sleep_duration -= previous_sleep_time;
1479
1480 // adjust system with 1 frame IF NECESSARY ....
1481 if (l1s.pw_mgr.sleep_duration)
1482 {
1483 /***************************************************/
1484 /* Fix Frame */
1485 /***************************************************/
1486 l1s_recover_Frame();
1487
1488 /***************************************************/
1489 /* Fix Os */
1490 /***************************************************/
1491 if (Cust_recover_Os()) l1s.pw_mgr.Os_ticks_required = TRUE;
1492 }
1493 }
1494 #endif
1495 }
1496
1497
1498 /*-------------------------------------------------------*/
1499 /* l1s_compute_wakeup_Ticks() */
1500 /*-------------------------------------------------------*/
1501 /* */
1502 /* Description: wake-up */
1503 /* ------------ */
1504 /* This function compute the sleep duration according to */
1505 /* current value of count down counter. */
1506 /* - if TIMER_VALUE = 0 it returns TIMER_INIT */
1507 /* - else it returns TIMER_INIT-TIMER_VALUE*/
1508 /* */
1509 /*-------------------------------------------------------*/
1510 BOOL l1s_compute_wakeup_ticks(void)
1511 {
1512 UWORD16 temp_clear_intr;
1513 #if (CODE_VERSION != SIMULATION)
1514 // read current value of count down counter
1515 l1s.pw_mgr.sleep_duration = READ_ULDP_TIMER_VALUE;
1516
1517 // if count down=0 it's a scheduled wake-up....
1518 if (l1s.pw_mgr.sleep_duration == 0)
1519 {
1520 // read sleeping planned value in TPU INIT register
1521 l1s.pw_mgr.sleep_duration = READ_ULDP_TIMER_INIT;
1522 // INTH is different from the ULPD interrupt -> aynchronous wakeup
1523 #if (CHIPSET == 12) || (CHIPSET == 15)
1524 if (int_id != C_INTH_TGSM_IT)
1525 #else
1526 if (int_id != IQ_TGSM)
1527 #endif
1528 {
1529 wakeup_type = WAKEUP_ASYNCHRONOUS_ULPD_0;
1530 // RESET IT_ULPD in ULPD module
1531 // The ULDP_GSM_TIMER_IT_REG is a read only register and is cleared on reading the register
1532 temp_clear_intr =(* (volatile UWORD16 *) ULDP_GSM_TIMER_IT_REG) & ULPD_IT_TIMER_GSM;
1533 #if (CHIPSET == 12) || (CHIPSET == 15)
1534 // RESET IQ_TGSM (IT_ULPD) in IT register
1535 F_INTH_RESET_ONE_IT(C_INTH_TGSM_IT);
1536 // RESET IQ_FRAME in IT register
1537 F_INTH_RESET_ONE_IT(C_INTH_FRAME_IT);
1538 int_id = C_INTH_TGSM_IT;
1539 #else
1540 // RESET IQ_TGSM (IT_ULPD) in IT register
1541 INTH_RESETONEIT(IQ_TGSM);
1542 // RESET IQ_FRAME in IT register
1543 INTH_RESETONEIT(IQ_FRAME);
1544 int_id = IQ_TGSM;
1545 #endif
1546 return(FALSE);
1547 }
1548 else
1549 return(FALSE);
1550 }
1551 else // Unscheduled wakeup
1552 {
1553 // read sleeping planned value in TPU INIT register & compute time elapsed
1554 l1s.pw_mgr.sleep_duration = READ_ULDP_TIMER_INIT - l1s.pw_mgr.sleep_duration;
1555 return(TRUE);
1556 }
1557 #else
1558 return(FALSE);//omaps00090550
1559 #endif
1560 }
1561
1562 /*-------------------------------------------------------*/
1563 /* l1s_recover_Frame() */
1564 /*-------------------------------------------------------*/
1565 /* */
1566 /* Description: adjust layer1 data from sleep duration */
1567 /* ------------ */
1568 /*-------------------------------------------------------*/
1569 void l1s_recover_Frame(void)
1570 {
1571 if (l1_config.pwr_mngt == PWR_MNGT)
1572 {
1573 /***************************************************/
1574 /* Fix Frame counters . */
1575 /***************************************************/
1576 l1s.debug_time += l1s.pw_mgr.sleep_duration; // used for debug and by L3 scenario.
1577
1578 // Time...
1579 // Update "actual time".
1580 l1s_increment_time(&(l1s.actual_time), l1s.pw_mgr.sleep_duration);
1581
1582 // Update "next time".
1583 l1s.next_time = l1s.actual_time;
1584 l1s_increment_time(&(l1s.next_time), 1); // Next time is actual_time + 1
1585
1586 #if L1_GPRS
1587 // Update "next plus time".
1588 l1s.next_plus_time = l1s.next_time;
1589 l1s_increment_time(&(l1s.next_plus_time), 1); // Next_plus time is next_time + 1
1590 #endif
1591
1592 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4)
1593 trace_fct(CST_L1S_ADJUST_TIME, (UWORD32)(-1));
1594 #endif
1595
1596 // Multiframe table...
1597 // Increment active frame % mftab size.
1598 l1s.afrm = (l1s.afrm + l1s.pw_mgr.sleep_duration) % MFTAB_SIZE;
1599
1600 // Control function counters...
1601 // Increment frame count from last AFC update.
1602 l1s.afc_frame_count+= l1s.pw_mgr.sleep_duration;
1603 // reset counter to mask SNR/TOA results for 2 fr.
1604 #if (TOA_ALGO == 2)
1605 l1s.toa_var.toa_snr_mask=0;
1606 #else
1607 l1s.toa_snr_mask=0;
1608 #endif
1609
1610 /***************************************************/
1611 /* Fix next L1S task counter */
1612 /***************************************************/
1613 // Decrement time to next L1S task.
1614 if((l1a_l1s_com.time_to_next_l1s_task > 0) &&
1615 (l1a_l1s_com.time_to_next_l1s_task < MAX_FN))
1616 l1a_l1s_com.time_to_next_l1s_task -= l1s.pw_mgr.sleep_duration;
1617 } // l1_config.pwr_mngt == PWR_MNGT
1618 }
1619
1620
1621 /*-------------------------------------------------------*/
1622 /* l1s_recover_HWTimers() */
1623 /*-------------------------------------------------------*/
1624 /* */
1625 /* Description: adjust hardware timers from sleep */
1626 /* ------------ duration */
1627 /* */
1628 /* Timers clocks are enabled after VTCX0+SLICER+13MHZ */
1629 /* setup times. So sleep duration is : */
1630 /* GSM TIMER - SETUP_FRAME + SETUP_SLICER + SETUP_VTCXO */
1631 /* + SETUP_CLK13 */
1632 /*-------------------------------------------------------*/
1633
1634 void l1s_recover_HWTimers(void)
1635 {
1636 #if (CODE_VERSION != SIMULATION)
1637
1638 #define SETUP_FRAME_IN_CLK32 (SETUP_FRAME*4.615*32.768)
1639 #if (CHIPSET == 15)
1640 #define DELTA_TIME (0)
1641 #else
1642 #define DELTA_TIME (SETUP_FRAME_IN_CLK32 -SETUP_SLICER - SETUP_VTCXO)
1643 #endif
1644
1645
1646 if (l1_config.pwr_mngt == PWR_MNGT)
1647 {
1648 WORD32 timer1,timer2,timer;
1649 #if (CHIPSET == 12) || (CHIPSET == 15)
1650 WORD32 timer_sec;
1651 #endif
1652 UWORD16 cntlreg;
1653 UWORD16 modereg;
1654 double duration;
1655
1656
1657 //WORD32 old;- OMAPS 90550 new
1658
1659 // read Hercules Timers & Watchdog
1660 //=================================================
1661 // Tint = Tclk * (LOAD_TIM+1) * 2^(PTV+1)
1662 // Tclk = 1.2308us for Fclk=13Mhz
1663 // PTV = 7 (pre-scaler field)
1664 //-------------------------------------------------
1665
1666 cntlreg = Dtimer1_Get_cntlreg();
1667 if ( (cntlreg & D_TIMER_RUN) == D_TIMER_RUN)
1668 {
1669 #if 0 /* match TCS211 object */
1670 cntlreg = cntlreg&0x1F;
1671 #endif
1672 cntlreg >>= 2; // take PTV
1673 cntlreg = 1 << (cntlreg+1); // compute 2^(PTV+1)
1674 // convert sleep duration in HWTimers ticks....
1675 duration = (l1s.pw_mgr.sleep_duration * 4.615 - (DELTA_TIME/32.768)) / (cntlreg * 0.0012308);
1676 #if 0 /* match TCS211 object */
1677 if (duration < 0.0){
1678 duration = 0.0; // This needs to be done for all the timers
1679 }
1680 #endif
1681 timer1 = Dtimer1_ReadValue() - (UWORD16) duration;
1682
1683 Dtimer1_Start(0);
1684 Dtimer1_WriteValue(timer1);
1685 Dtimer1_Start(1);
1686 }
1687
1688 cntlreg = Dtimer2_Get_cntlreg();
1689 if ( (cntlreg & D_TIMER_RUN) == D_TIMER_RUN)
1690 {
1691 #if 0 /* match TCS211 object */
1692 cntlreg = cntlreg&0x1F;
1693 #endif
1694 cntlreg >>= 2; // take PTV
1695 cntlreg = 1 << (cntlreg+1);
1696 // convert sleep duration in HWTimers ticks....
1697 duration = (l1s.pw_mgr.sleep_duration * 4.615 - (DELTA_TIME/32.768)) / (cntlreg * 0.0012308);
1698 #if 0 /* match TCS211 object */
1699 if (duration < 0.0){
1700 duration = 0.0; // This needs to be done for all the timers
1701 }
1702 #endif
1703 timer2 = Dtimer2_ReadValue() - (UWORD16) duration;
1704 Dtimer2_Start(0);
1705 Dtimer2_WriteValue(timer2);
1706 Dtimer2_Start(1);
1707 }
1708
1709 cntlreg = TIMER_Read(0);
1710 modereg = TIMER_Read(2);
1711 if ( (cntlreg & TIMER_ST) || (modereg & TIMER_WDOG))
1712 {
1713 // in watchdog mode PTV is forced to 7
1714 if ( modereg & TIMER_WDOG )
1715 cntlreg |= TIMER_PTV;
1716
1717 cntlreg = (cntlreg & TIMER_PTV) >> 9; // take PTV
1718 cntlreg = 1 << (cntlreg+1);
1719 // convert sleep duration in HWTimers ticks....
1720 duration = (l1s.pw_mgr.sleep_duration * 4.615 - (DELTA_TIME/32.768)) / (cntlreg * 0.001078);
1721
1722 timer = TIMER_ReadValue() - (UWORD16) duration;
1723 TIMER_START_STOP(0);
1724 TIMER_WriteValue(timer);
1725 TIMER_START_STOP(1);
1726 }
1727
1728 #if (CHIPSET == 12) || (CHIPSET == 15)
1729 cntlreg = TIMER_SEC_Read(0);
1730 modereg = TIMER_SEC_Read(2);
1731 if ( (cntlreg & TIMER_ST) || (modereg & TIMER_WDOG))
1732 {
1733 // in watchdog mode PTV is forced to 7
1734 if ( modereg & TIMER_WDOG )
1735 cntlreg |= TIMER_PTV;
1736
1737 cntlreg = (cntlreg & TIMER_PTV) >> 9; // take PTV
1738 cntlreg = 1 << (cntlreg+1);
1739 // convert sleep duration in HWTimers ticks....
1740 duration = (l1s.pw_mgr.sleep_duration * 4.615 - (DELTA_TIME/32.768)) / (cntlreg * 0.001078);
1741
1742 timer_sec = TIMER_SEC_ReadValue() - (UWORD16) duration;
1743 TIMER_SEC_START_STOP(0);
1744 TIMER_SEC_WriteValue(timer_sec);
1745 TIMER_SEC_START_STOP(1);
1746 }
1747 #endif
1748
1749 }
1750 #endif
1751 }
1752 /*-------------------------------------------------------*/
1753 /* l1s_get_next_gauging_in_Packet_Idle() */
1754 /*-------------------------------------------------------*/
1755 /* */
1756 /* Description: */
1757 /* ------------ */
1758 /* return the nbr of frames before the next gauging */
1759 /* return -1 means no activity planned */
1760 /*-------------------------------------------------------*/
1761 #if L1_GPRS
1762 UWORD32 next_gauging_scheduled_for_PNP; // gauging for Packet Idle
1763
1764 WORD32 l1s_get_next_gauging_in_Packet_Idle(void)
1765 {
1766 WORD32 next_gauging;
1767
1768 // gauging performed with Normal Paging (we are in Idle mode)
1769 if (l1a_l1s_com.l1s_en_task[NP] == TASK_ENABLED)
1770 return (-1); // no activity planned
1771
1772 // we are not in Packet Idle Mode
1773 if (l1a_l1s_com.l1s_en_task[PNP] != TASK_ENABLED)
1774 return (-1); // no activity planned
1775
1776 next_gauging = next_gauging_scheduled_for_PNP - l1s.actual_time.fn ;
1777 if (next_gauging < 0)
1778 next_gauging+=MAX_FN;
1779
1780 if (next_gauging <= MIN_SLEEP_TIME)
1781 return(0);
1782
1783 return (next_gauging);
1784 }
1785 #endif
1786 /*-------------------------------------------------------*/
1787 /* l1s_gauging_decision_with_PNP() */
1788 /*-------------------------------------------------------*/
1789 /* */
1790 /* Description: */
1791 /* ------------ */
1792 /* */
1793 /*-------------------------------------------------------*/
1794 #if L1_GPRS
1795 BOOL l1s_gauging_decision_with_PNP(void)
1796 {
1797 #define TWO_SECONDS_IN_FRAME (UWORD16)(2000/4.615)
1798
1799 /* reconstructed TCS211 code */
1800 if (l1s.actual_time.fn >= next_gauging_scheduled_for_PNP)
1801 {
1802 next_gauging_scheduled_for_PNP = l1s.actual_time.fn + TWO_SECONDS_IN_FRAME;
1803 if (next_gauging_scheduled_for_PNP >= MAX_FN) next_gauging_scheduled_for_PNP -= MAX_FN;
1804 return (TRUE);
1805 }
1806
1807 return (FALSE); // do not perform gauging
1808 }
1809 #endif
1810 /*-------------------------------------------------------*/
1811 /* l1s_gauging_decision_with_NP() */
1812 /*-------------------------------------------------------*/
1813 /* */
1814 /* Description: */
1815 /* ------------ */
1816 /* */
1817 /*-------------------------------------------------------*/
1818 BOOL l1s_gauging_decision_with_NP(void)
1819 {
1820
1821 static UWORD8 time_to_gaug;
1822
1823 // a paging is scheduled or , was scheduled but discarded by a higher priority task
1824 if (l1s.pw_mgr.paging_scheduled == TRUE)
1825 {
1826 l1s.pw_mgr.paging_scheduled = FALSE; // reset Flag.
1827
1828 // A gauging session is needed : start gauging session with this paging bloc !
1829
1830 //Nina modify to save power, not forbid deep sleep, only force gauging in next paging
1831 // FreeCalypso TCS211 reconstruction: Nina's change reverted
1832 #if 1
1833 if (l1s.pw_mgr.enough_gaug != TRUE)
1834 time_to_gaug = 0;
1835 #else
1836 if ((l1s.pw_mgr.enough_gaug != TRUE)||(l1s.force_gauging_next_paging_due_to_CCHR == 1))
1837 {
1838 time_to_gaug = 0;
1839 l1s.force_gauging_next_paging_due_to_CCHR = 0;
1840 }
1841 #endif
1842 if (time_to_gaug > 0)
1843 {
1844 time_to_gaug--; // perform the gauging with an another paging.
1845 }
1846 else // perform the gauging with this paging
1847 {
1848 if (l1s.task_status[NP].current_status == ACTIVE )
1849 {
1850 time_to_gaug = GAUG_VS_PAGING_RATE[l1a_l1s_com.bs_pa_mfrms-2]-1;
1851
1852 return (TRUE); // gauging allowed
1853 }
1854 else // a gauging is scheduled to be perform here but the paging is missing
1855 { // (paging discarded by a higher priority task ?)
1856 l1s.pw_mgr.enough_gaug= FALSE; // forbid Deep sleep until next gauging
1857 }
1858 }
1859 }
1860 return (FALSE); // gauging not allowed
1861 }
1862
1863 /*************************************************************/
1864 /* Gauging task management : */
1865 /* */
1866 /* CALYPSO */
1867 /* */
1868 /* 9 8 7 6 5 4 3 2 1 0 */
1869 /* C0 C1 C2 C3 C4 W R - - - */
1870 /* | | */
1871 /* | | */
1872 /* |_ start gauging |_ stop gauging */
1873 /* */
1874 /*OTHERS: */
1875 /* */
1876 /* 11 10 9 8 7 6 5 4 3 2 1 0 */
1877 /* C0 C1 C2 C3 C4 W R - - - - - */
1878 /* | | | | | */
1879 /* | | |_ start gauging |_ stop gauging */
1880 /* | | | | */
1881 /* | |_ (ITCOM) | |(ITCOM) */
1882 /* | | */
1883 /* |_ pgm PLL |_restore PLL */
1884 /* */
1885 /* */
1886 /*************************************************************/
1887 void l1s_gauging_task(void)
1888 {
1889 if (l1_config.pwr_mngt == PWR_MNGT)
1890 {
1891 /*************************************************************/
1892 if (l1s.pw_mgr.gauging_task == ACTIVE)
1893 {
1894 /*************************************************************/
1895 // COUNT = 10 ==> PLL is at 65 Mhz, start the gauging
1896 /*************************************************************/
1897 #if (CHIPSET==7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15)
1898 // the gauging was started with the begining of the paging
1899 #else
1900 if (l1s.pw_mgr.gaug_count == (l1s.pw_mgr.gaug_duration-1))
1901 {
1902 #if (CODE_VERSION != SIMULATION)
1903 ULDP_GAUGING_START; // start gauging
1904 #endif
1905
1906 #if (TRACE_TYPE != 0)
1907 #if (GSM_IDLE_RAM != 0)
1908 l1_trace_gauging_intram();
1909 #else
1910 l1_trace_gauging();
1911 #endif
1912 #endif
1913 }
1914 #endif
1915
1916 l1s.pw_mgr.gaug_count--; // decrement counter
1917
1918
1919 // When a MISC task is enabled L1S must be ran every frame
1920 // to be able to enable the frame interrupt for DSP
1921 l1a_l1s_com.time_to_next_l1s_task = 0;
1922 }
1923
1924 /*************************************************************/
1925 // REQUEST A GAUGING PROCESS ON EACH PAGING BLOCK
1926 // IN IDLE MODE .....
1927 /*************************************************************/
1928
1929 else if (l1s.pw_mgr.gauging_task == INACTIVE )
1930 {
1931 BOOL decision = FALSE;
1932
1933 if (l1a_l1s_com.l1s_en_task[NP] == TASK_ENABLED)
1934 decision = l1s_gauging_decision_with_NP();
1935 #if L1_GPRS
1936 else
1937 if (l1a_l1s_com.l1s_en_task[PNP] == TASK_ENABLED)
1938 decision = l1s_gauging_decision_with_PNP();
1939 #endif
1940
1941 if (decision == TRUE)
1942 {
1943 // gauging duration
1944 l1s.pw_mgr.gaug_count = l1s.pw_mgr.gaug_duration;
1945
1946 #if (CHIPSET==7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15)
1947 // start ULPD gauging immediately with Calypso because we needn't IT_COM.
1948 #if (CODE_VERSION != SIMULATION)
1949 ULDP_GAUGING_START;
1950 #if (CHIPSET == 12) || (CHIPSET == 15)
1951 // Force the DPLL to be active
1952 ( * (volatile SYS_UWORD16 *) CLKM_CNTL_CLK) &= ~(CLKM_DPLL_DIS);
1953 #endif
1954 #endif
1955
1956 #if (TRACE_TYPE != 0)
1957 #if (GSM_IDLE_RAM != 0)
1958 l1_trace_gauging_intram();
1959 #else
1960 l1_trace_gauging();
1961 #endif
1962 #endif
1963 #endif
1964
1965 // DSP programmation .......
1966 #if (DSP >= 33)
1967 #if (CHIPSET==4)
1968 l1s_dsp_com.dsp_ndb_ptr->d_pll_config |= B_32KHZ_CALIB;
1969 #endif
1970 #else
1971 l1s_dsp_com.dsp_ndb_ptr->d_pll_clkmod1 = CLKMOD2; // IDLE1 only for DSP
1972 #endif
1973
1974 l1s.pw_mgr.gauging_task = ACTIVE;
1975 }
1976 }
1977 }
1978 }
1979 /*-------------------------------------------------------*/
1980 /* l1s_gauging_task_end() */
1981 /*-------------------------------------------------------*/
1982 /* */
1983 /* Description: */
1984 /* ------------ */
1985 /* stop the gauging activity */
1986 /*-------------------------------------------------------*/
1987 void l1s_gauging_task_end(void)
1988 {
1989 if (l1_config.pwr_mngt == PWR_MNGT)
1990 {
1991 /*************************************************************/
1992 if (l1s.pw_mgr.gauging_task == ACTIVE)
1993 {
1994 /*************************************************************/
1995 // COUNT = 1 ==> stop the gauging and free DSP idle modes....
1996 /*************************************************************/
1997 if (l1s.pw_mgr.gaug_count == 1)
1998 {
1999 // wait for end of gauging interrupt ...
2000 l1s.pw_mgr.gauging_task = WAIT_IQ;
2001
2002 // Unmask ULPD GAUGING int.
2003 #if (CODE_VERSION != SIMULATION)
2004 #if (CHIPSET == 12) || (CHIPSET == 15)
2005 F_INTH_ENABLE_ONE_IT(C_INTH_ULPD_GAUGING_IT);
2006 #else
2007 INTH_ENABLEONEIT(IQ_ULPD_GAUGING);
2008 #endif
2009 ULDP_GAUGING_STOP; // stop ULPD gauging
2010 #if (CHIPSET == 12) || (CHIPSET == 15)
2011 // Allow the DPLL to be cut according to ARM sleep mode
2012 //( * (volatile SYS_UWORD16 *) CLKM_CNTL_CLK) |= (CLKM_DPLL_DIS);
2013 #endif
2014 #endif
2015
2016 // DSP programmation : free IDLE modes...
2017 #if (DSP >= 33)
2018 #if (CHIPSET==4)
2019 l1s_dsp_com.dsp_ndb_ptr->d_pll_config &= ~B_32KHZ_CALIB;
2020 #endif
2021 #else
2022 l1s_dsp_com.dsp_ndb_ptr->d_pll_clkmod1 = CLKMOD1;
2023 #endif
2024
2025
2026 #if (CODE_VERSION == SIMULATION)
2027 // in order to simulate the Gauging interrupt
2028 GAUGING_Handler();
2029
2030 #if (TRACE_TYPE==5)
2031 trace_ULPD("Stop Gauging", l1s.actual_time.fn);
2032 #endif
2033 #endif
2034 }
2035 }
2036 }
2037 }
2038
2039 //#pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_END
2040 #endif