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comparison src/cs/system/bootloader/src/bootloader.s @ 605:07d0dc4431f4

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bootloader.s: same MEMIF fix as in int.s plus DPLL BYPASS fix Both MEMIF and DPLL settings are now the same between int.s and bootloader.s assembly code paths. Previously bootloader.s was setting DPLL BYPASS /2 mode, which persisted until _INT_Initialize code with the bootloader body omitted, or was changed to /1 in the hardware init function in the bootloader.lib:start.obj module.
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 17 Jun 2019 18:40:32 +0000
parents 945cf7f506b2
children
comparison
equal deleted inserted replaced
604:a7ed7d4483b0 605:07d0dc4431f4
159 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable 159 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
160 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable 160 CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
161 .endif 161 .endif
162 162
163 .elseif BOARD = 41 ; D-Sample FLASH CS0 163 .elseif BOARD = 41 ; D-Sample FLASH CS0
164
165 ; FreeCalypso change, please see MEMIF-wait-states document
166 ; in the freecalypso-docs repository for the explanation.
167
168 .if VCXO_26MHZ = 1
169 CS0_MEM_REG .short 0x2a2 ; 1 Dummy Cycle 16 bit 2 WS SW BP enable
170 CS1_MEM_REG .short 0x2a2 ; 1 Dummy Cycle 16 bit 2 WS SW BP enable
171 CS2_MEM_REG .short 0x2a2 ; 1 Dummy Cycle 16 bit 2 WS SW BP enable
172 .else
164 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable 173 CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
165 CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable 174 CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
166 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable 175 CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
176 .endif
167 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable 177 CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
168 CS4_MEM_REG .short 0x281 ; 1 Dummy Cycle 8 bit 1 WS SW BP enable 178 CS4_MEM_REG .short 0x281 ; 1 Dummy Cycle 8 bit 1 WS SW BP enable
169 179
170 .if CHIPSET = 8 180 .if CHIPSET = 8
171 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable 181 CS6_MEM_REG .short 0x0c0 ; 0 Dummy Cycle 32 bit 0 WS SW BP enable
250 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address 260 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address
251 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address 261 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address
252 262
253 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register 263 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
254 ; Use DPLL, Divide by 1 264 ; Use DPLL, Divide by 1
255 DPLL_CONTROL_RST .short 0x2006 ; Configure DPLL in default state 265 DPLL_CONTROL_RST .short 0x2002 ; Configure DPLL in BYPASS mode, /1
256 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module 266 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module
257 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled 267 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled
258 268
259 .elseif CHIPSET = 10 269 .elseif CHIPSET = 10
260 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address 270 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
262 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address 272 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address
263 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address 273 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address
264 274
265 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register 275 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
266 ; Use DPLL, Divide by 1 276 ; Use DPLL, Divide by 1
267 DPLL_CONTROL_RST .short 0x2006 ; Configure DPLL in default state 277 DPLL_CONTROL_RST .short 0x2002 ; Configure DPLL in BYPASS mode, /1
268 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module 278 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module
269 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled 279 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled
270 280
271 .elseif CHIPSET = 11 281 .elseif CHIPSET = 11
272 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address 282 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address
274 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address 284 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address
275 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address 285 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address
276 286
277 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register 287 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register
278 ; Use DPLL, Divide by 1 288 ; Use DPLL, Divide by 1
279 DPLL_CONTROL_RST .short 0x2006 ; Configure DPLL in default state 289 DPLL_CONTROL_RST .short 0x2002 ; Configure DPLL in BYPASS mode, /1
280 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module 290 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module
281 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled 291 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled
282 292
283 .elseif CHIPSET = 12 293 .elseif CHIPSET = 12
284 DBG_DMA_P2 .word 0xFFFEF02C ; DBG_DMA_P2 register address 294 DBG_DMA_P2 .word 0xFFFEF02C ; DBG_DMA_P2 register address