annotate src/cs/drivers/drv_core/clkm/clkm.c @ 638:cab2f315827e

FFS dev.c: added Spansion PL032J to the "generic" table With the discovery of first GTM900 and then Tango, it now appears that Openmoko was not the only manuf after all who kept TI's TCS211 firmware largely intact (as opposed to changing it beyond all recognition like Compal, Chi-Mei and BenQ did), thus we are now getting new "alien" targets on which we reuse the original manuf's FFS with IMEI and RF calibration tables as if it were native. On these targets we use the original device table for FFS, even though we previously thought that it would never apply to any target other than dsample, leonardo and gtamodem. We have previously added Samsung K5L33xxCAM (a new kind of multi-ID device) to the generic table to support its use in Huawei GTM900-B modules; now we got news that some slightly older GTM900-B specimen used S71PL032J instead, so we are now adding PL032J as well.
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 30 Jan 2020 17:45:48 +0000
parents 945cf7f506b2
children
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1 /******************************************************************************
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2 TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
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3
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4 Property of Texas Instruments -- For Unrestricted Internal Use Only
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5 Unauthorized reproduction and/or distribution is strictly prohibited. This
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6 product is protected under copyright law and trade secret law as an
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7 unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All
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8 rights reserved.
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9
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10
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11 Filename : clkm.c
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12
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13 Description : Set of functions useful to test the Saturn
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14 CLKM peripheral
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15
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16 Project : drivers
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17
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18 Author : pmonteil@tif.ti.com Patrice Monteil.
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19
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20 Version number : 1.13
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21
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
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22 Date : 05/23/03
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23
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24 Previous delta : 10/23/01 14:43:31
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25
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26 Sccs Id (SID) : '@(#) clkm.c 1.11 10/23/01 14:43:31 '
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27
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28 *****************************************************************************/
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29
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30 //############################################################
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31 //############################################################
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32 //### Be careful: this file must be placed in Flash Memory ###
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33 //### and compiled in 16 bits length intructions ###
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34 //### (CF. the function wait_ARM_cycles() ###
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35 //############################################################
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36 //############################################################
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37
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38 #include "l1sw.cfg"
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39 #include "chipset.cfg"
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40 #include "board.cfg"
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41 #include "swconfig.cfg"
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42
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43 #if (OP_L1_STANDALONE == 0)
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44 #include "main/sys_types.h"
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45 #else
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46 #include "sys_types.h"
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47 #endif
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48
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49 #include "clkm.h"
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50
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51
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52 #if (CHIPSET == 12)
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53 #include "sys_memif.h"
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54 #else
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55 #include "memif/mem.h"
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56 #endif
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57
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58 #if (BOARD == 34)
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59 #include "armio/armio.h"
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60 #include "timer/timer.h"
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61 #endif
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62
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63 static SYS_UWORD32 ratio_wait_loop = 0;
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64
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65 #if (CHIPSET == 12)
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66 const double dsp_div_value[CLKM_NB_DSP_DIV_VALUE] = {1, 1.5, 2, 3};
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67 #endif
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68
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69 #if (BOARD == 34)
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70 /*
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71 * CLKM_InitARMClock()
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72 *
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73 * This init is for VTCX0 = 13 MHz
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74 * (use CLKM_VTCXO_26 if VTCX0 is 26 MHz)
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75 * Parameters : src : 0x0 means EXT CLK (mpu dpll) selected
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76 * 0x1 means VTCX0 selected
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77 * div : Division factor applied to clock
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78 * source
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79 * (div = 3 -> divise by 3/2 in fact)
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80 * WARNING : reverse order in comparison to ULYSSE
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81 *
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82 * Return : none
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83 * Functionality :Initialize the ARM Clock frequency
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84 */
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85
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86 void CLKM_InitARMClock(int src, int div)
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87 {
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88 SYS_UWORD16 cntl = * (volatile SYS_UWORD16 *) CLKM_ARM_CLK;
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89 int clk_xp5, clk_div;
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90
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91 if (div == 3)
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92 clk_xp5 = 1;
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93 else
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94 clk_xp5 = 0;
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95
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96 if (div == 2)
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97 clk_div = 1;
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98 else if (div == 4)
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99 clk_div = 0;
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100 else
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101 clk_div = 3;
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102
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103 cntl &= ~(MASK_ARM_MCLK_1P5 | CLKM_MCLK_DIV);
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104 cntl |= ((clk_xp5 << 3) | (clk_div << 4));
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105
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106 * (volatile SYS_UWORD16 *) CLKM_ARM_CLK = cntl;
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107 if (src)
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108 CLKM_EnableDPLL(0);
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109 else
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110 CLKM_EnableDPLL(1);
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111 }
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112
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113 /*
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114 * CLKM_SetMclkDiv
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115 *
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116 * Set divider
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117 *
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118 * Parameter : 2-bit divider as per spec (0-7)
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119 *
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120 * Side-effect : compute magic delay for busy loops
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121 *
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122 */
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123 void CLKM_SetMclkDiv(int div)
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124 {
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125 volatile SYS_UWORD16 clkm_ctrl;
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126 clkm_ctrl = *((volatile SYS_UWORD16 *) CLKM_ARM_CLK); // read register
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127 clkm_ctrl &= ~CLKM_MCLK_DIV;
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128 clkm_ctrl |= (div << 4);
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129 *((volatile SYS_UWORD16 *) CLKM_ARM_CLK) = clkm_ctrl;
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130 }
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131
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132 /*
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133 * CLKM_EnableDPLL
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134 *
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135 * Enable or disable 48mhz PLL for ARM clock
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136 *
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137 * Parameter : 1 or 0
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138 *
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139 * Side-effect : compute magic delay for busy loops
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140 *
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141 */
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142 void CLKM_EnableDPLL(int enable)
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143 {
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144 volatile SYS_UWORD16 clkm_ctrl;
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145
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146 // read CLKM register
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147 clkm_ctrl = *((volatile SYS_UWORD16 *) CLKM_ARM_CLK);
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148
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149 if (enable)
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150 {
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151 // PARAMETERS tuned for the AVENGER 2 reference design
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152 // we wait before accessing external memory at wake up
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153 // we have 2.5 ms margin before the first IT TDMA, we wait
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154 //
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155 // 5000 loop cycles
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156 // 5000 * 5 arm7 cycles
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157 // giving <= 1 ms at 26 MHz
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158 //
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159 wait_ARM_cycles(5000);
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160 }
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161 else
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162 {
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163 // reset bit for VTCXO
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164 clkm_ctrl &= ~CLKM_CLKIN_SEL;
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165 *((volatile SYS_UWORD16 *) CLKM_ARM_CLK) = clkm_ctrl;
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166
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167 // disable clk48mhz
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168 AI_ResetBit(6);
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169 }
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170 }
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171
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172 /*
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173 * CLKM_EnableSharedMemClock
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174 *
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175 * Enable or disable shared mem clock
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176 *
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177 * Parameter : 1 or 0
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178 *
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179 */
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180 void CLKM_EnableSharedMemClock(int enable)
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181 {
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182 if (enable)
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183 {
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184 // request shared mem clock and wait for MPU HW acknowledge
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185 AI_ResetBit(4);
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186 while(AI_ReadBit(5)!=1);
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187 }
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188 else
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189 {
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190 // disable shared mem clock
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191 AI_SetBit(4);
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192 }
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193 }
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194
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195 /*
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196 * CLKM_InitLeadClock
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197 *
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198 * Parameter : onoff, mul, ndiv, div
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199 *
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200 * onoff -> (1:pll on) (0: pll off)
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201 * if div = 0 -> x(plmul+1)
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202 * if div = 1 -> x(plmul+1)/2 if plmul is even
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203 * x(plmul/4) if plmul is odd
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204 * ndiv
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205 */
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206
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207 void CLKM_InitLeadClock(int onoff, int mul, int ndiv, int div)
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208 {
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209 int pldiv, pllndiv ;
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210 SYS_UWORD16 value = 0;
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211
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212 value |= onoff & CLKM_PLONOFF ;
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213 value |= (mul << 1) & CLKM_PLMUL;
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214 value |= (ndiv << 5)& CLKM_PLLNDIV;
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215 value |= (div << 6) & CLKM_PLDIV;
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216
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217 CLKM_INITLEADPLL(value);
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218 }
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219
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220 #elif ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
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221 /*--------------------------------------------------------------*/
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222 /* CLKM_InitARMClock() */
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223 /*--------------------------------------------------------------*/
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224 /* Parameters : clk_src : 0x00 means DPLL selected */
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225 /* 0x01 means VTCX0 selected */
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226 /* 0x03 means CLKIN selected */
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227 /* clk_xp5 : Enable 1.5 or 2.5 division factor */
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228 /* (0 or 1) */
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229 /* clk_div : Division factor applied to clock */
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230 /* source */
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231 /* WARNING : reverse order in comparison to ULYSSE */
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232 /* */
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233 /* Return : none */
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234 /* Functionality :Initialize the ARM Clock frequency */
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235 /*--------------------------------------------------------------*/
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236 void CLKM_InitARMClock(SYS_UWORD16 clk_src, SYS_UWORD16 clk_div, SYS_UWORD16 clk_xp5)
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237 {
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238 SYS_UWORD16 cntl = * (volatile SYS_UWORD16 *) CLKM_ARM_CLK;
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239
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240 cntl &= ~(CLKM_CLKIN0 | CLKM_CLKIN_SEL | CLKM_ARM_MCLK_XP5 | CLKM_MCLK_DIV);
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241
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242 cntl |= ((clk_src << 1) | (clk_xp5 << 3) | (clk_div << 4));
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243
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244 * (volatile SYS_UWORD16 *) CLKM_ARM_CLK = cntl;
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245 }
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246 #else
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247 /*--------------------------------------------------------------
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248 * CLKM_InitARMClock()
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249 *--------------------------------------------------------------
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250 * Parameters : clk_src : 0x00 means CLKIN selected
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251 * 0x01 means 32 K selected
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252 * 0x02 means External clock selected
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253 *
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254 * Return : none
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255 * Functionality :Initialize the ARM Clock frequency
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256 *--------------------------------------------------------------*/
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257 void CLKM_InitARMClock(SYS_UWORD16 clk_src, SYS_UWORD16 clk_div)
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258 {
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259 SYS_UWORD16 cntl = * (volatile SYS_UWORD16 *) CLKM_ARM_CLK;
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260
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261 cntl &= ~(CLKM_LOW_FRQ | CLKM_CLKIN_SEL | CLKM_MCLK_DIV);
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262
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263 cntl |= ((clk_src << 1) | (clk_div << 4));
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264
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265 * (volatile SYS_UWORD16 *) CLKM_ARM_CLK = cntl;
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266 }
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267
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268 #endif
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269
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270
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271 /*-------------------------------------------------------*/
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272 /* convert_nanosec_to_cycles() */
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273 /*-------------------------------------------------------*/
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274 /* parameter: time in 10E-9 seconds */
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275 /* return: Number of cycles for the wait_ARM_cycles() */
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276 /* function */
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277 /* */
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278 /* Description: */
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279 /* ------------ */
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280 /* convert x nanoseconds in y cycles used by the ASM loop*/
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281 /* function . Before calling this function, call the */
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282 /* initialize_wait_loop() function */
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283 /* Called when the HardWare needs time to wait */
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284 /*-------------------------------------------------------*/
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285 SYS_UWORD32 convert_nanosec_to_cycles(SYS_UWORD32 time)
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286 {
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287 return( time / ratio_wait_loop);
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288 }
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289
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290
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291 /*-------------------------------------------------------*/
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292 /* initialize_wait_loop() */
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293 /*-------------------------------------------------------*/
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294 /* */
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295 /* Description: */
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296 /* ------------ */
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297 /* Init the ratio used to convert time->Cycles according */
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298 /* to hardware parameters */
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299 /* measurement time for this function (ARM 39Mhz, 3 waits*/
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300 /* states) = 75 micoseconds */
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301 /*-------------------------------------------------------*/
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302
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303 void initialize_wait_loop(void)
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304 {
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305 #if (BOARD == 34)
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306 unsigned long ulTimeSpent=0;
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307
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308 // set up timer 2 for wait_ARM_cycles function calibration
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309 TM_EnableTimer (2);
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310 TM_ResetTimer (2, 0xFFFF, 0, 0);
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311
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312 // run wait_ARM_cycles() for 10000 loops
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313 wait_ARM_cycles(10000);
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314
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315 // time spent expressed in timer cycles
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316 // where 1 timer cycle = 2462 ns with prescale 0
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317 // 13 MHz divided by 16 = timer clkin
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318 // prescale 0 -> divided by 2
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319 ulTimeSpent = TM_ReadTimer (2);
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320
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321 TM_StopTimer (2);
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322
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323 ulTimeSpent = 0xFFFF - ulTimeSpent;
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324 ulTimeSpent *= 2462;
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325
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326 // compute ratio_wait_loop
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327 ratio_wait_loop = (unsigned long)(ulTimeSpent/10000.);
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328 #else
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329 #define NBR_CYCLES_IN_LOOP 5 // this value is got from an oscilloscope measurement
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330
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331 double src_ratio;
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332 double final_ratio;
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333
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334 SYS_UWORD16 flash_access_size;
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335 SYS_UWORD16 flash_wait_state;
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336 SYS_UWORD32 nbr;
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337 SYS_UWORD32 arm_clock;
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338
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339 //////////////////////////////////
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340 // compute the ARM clock used //
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341 //////////////////////////////////
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342 {
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343 SYS_UWORD16 arm_mclk_xp5;
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344 SYS_UWORD16 arm_ratio;
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345 SYS_UWORD16 clk_src;
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346 SYS_UWORD16 clkm_cntl_arm_clk_reg = * (volatile SYS_UWORD16 *) CLKM_CNTL_ARM_CLK;
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347
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348 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
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349 clk_src = (clkm_cntl_arm_clk_reg & MASK_CLKIN) >> 1;
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350 switch (clk_src)
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351 {
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352 case 0x00: //DPLL selected
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353 // select the DPLL factor
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354 #if (CHIPSET == 12)
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355 if (((* (volatile SYS_UWORD16 *) C_MAP_DPLL_BASE) & DPLL_LOCK) != 0)
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356 #else
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357 if (((* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR) & DPLL_LOCK) != 0)
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358 #endif
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359 {
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360 SYS_UWORD16 dpll_div;
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361 SYS_UWORD16 dpll_mul;
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362
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diff changeset
363 dpll_div=DPLL_READ_DPLL_DIV;
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364 dpll_mul=DPLL_READ_DPLL_MUL;
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365 src_ratio = (double)(dpll_mul)/(double)(dpll_div+1);
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366 }
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367 else // DPLL in bypass mode
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diff changeset
368 {
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369 SYS_UWORD16 dpll_div = DPLL_BYPASS_DIV;
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370 src_ratio= (double)(1)/(double)(dpll_div+1);
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diff changeset
371 }
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372 break;
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373 case 0x01: //VTCX0 selected
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diff changeset
374 src_ratio = 1;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
375 break;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
376 case 0x03: //CLKIN selected (external clock)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
377 src_ratio = 1;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
378 break;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
379 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
380 // define the division factor applied to clock source (CLKIN or VTCXO or DPLL)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
381 arm_ratio = (clkm_cntl_arm_clk_reg & CLKM_MCLK_DIV) >> 4;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
382
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
383 // check if the 1.5 or 2.5 division factor is enabled
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
384 arm_mclk_xp5 = clkm_cntl_arm_clk_reg & CLKM_ARM_MCLK_XP5;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
385
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
386 if (arm_mclk_xp5 == 0) // division factor enable for ARM clock ?
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
387 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
388 if (arm_ratio == 0)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
389 arm_ratio =1;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
390 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
391 else
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
392 arm_ratio = ((arm_ratio>>1) & 0x0001) == 0 ? 1.5 : 2.5;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
393
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
394
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
395 #else
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
396 src_ratio = 1;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
397
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
398 // define the division factor applied to clock source (CLKIN or VTCXO or DPLL)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
399 arm_ratio = (clkm_cntl_arm_clk_reg & CLKM_MCLK_DIV) >> 4;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
400
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
401 // check if the 1.5 or 2.5 division factor is enabled
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
402 arm_mclk_xp5 = clkm_cntl_arm_clk_reg & MASK_ARM_MCLK_1P5;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
403
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
404 if (arm_mclk_xp5 == 1) // division factor enable for ARM clock ?
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
405 arm_ratio = 1.5;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
406 else
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
407 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
408 if (arm_ratio == 0)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
409 arm_ratio = 4;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
410 else
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
411 if (arm_ratio == 1 )
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
412 arm_ratio = 2;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
413 else
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
414 arm_ratio = 1;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
415 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
416
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
417 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
418
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
419 final_ratio = (src_ratio / (double) arm_ratio);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
420
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
421 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
422 //////////////////////////////////////////
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
423 // compute the Flash wait states used //
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
424 //////////////////////////////////////////
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
425
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
426 #if (CHIPSET == 12)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
427 flash_access_size = 1;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
428 #else
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
429 flash_access_size = *((volatile SYS_UWORD16 *) MEM_REG_nCS0);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
430 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
431 flash_access_size = (flash_access_size >> 5) & 0x0003; // 0=>8bits, 1=>16 bits, 2 =>32 bits
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
432
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
433 // the loop file is compiled in 16 bits it means
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
434 // flash 8 bits => 2 loads for 1 16 bits assembler instruction
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
435 // flash 16 bits => 1 loads for 1 16 bits assembler instruction
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
436 // flash/internal RAM 32 bits => 1 loads for 1 16 bits assembler instruction (ARM bus 16 bits !!)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
437
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
438 // !!!!!!!!! be careful: if this file is compile in 32 bits, change these 2 lines here after !!!
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
439 if (flash_access_size == 0) flash_access_size = 2;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
440 else flash_access_size = 1;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
441
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
442 #if (CHIPSET == 12)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
443 /*
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
444 * loop move to run in internal memory, due to page mode in external memory
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
445 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
446 flash_wait_state = 0;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
447 #else
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
448 flash_wait_state = *((volatile SYS_UWORD16 *) MEM_REG_nCS0);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
449 flash_wait_state &= 0x001F;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
450 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
451
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
452 //////////////////////////////////////
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
453 // compute the length of the loop //
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
454 //////////////////////////////////////
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
455
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
456 // Number of flash cycles for the assembler loop
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
457 nbr = NBR_CYCLES_IN_LOOP;
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
458
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
459 // Number of ARM cycles for the assembler loop
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
460 nbr = nbr * (flash_wait_state + 1) * (flash_access_size);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
461
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
462 // time for the assembler loop (unit nanoseconds: 10E-9)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
463 arm_clock = final_ratio * 13; // ARM clock in Mhz
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
464 ratio_wait_loop = (SYS_UWORD32)((nbr*1000) / arm_clock);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
465 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
466 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
467
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
468 #if (CHIPSET != 12)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
469
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
470 /*-------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
471 /* wait_ARM_cycles() */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
472 /*-------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
473 /* */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
474 /* Description: */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
475 /* ------------ */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
476 /* Called when the HardWare needs time to wait. */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
477 /* this function wait x cycles and is used with the */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
478 /* convert_nanosec_to_cycles() & initialize_wait_loop() */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
479 /* */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
480 /* Exemple: wait 10 micro seconds: */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
481 /* initialize_wait_loop(); */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
482 /* wait_ARM_cycles(convert_nanosec_to_cycles(10000)) */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
483 /* */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
484 /* minimum time value with cpt_loop = 0 (estimated) */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
485 /* and C-SAMPLE / flash 6,5Mhz ~ 1,5 micro seconds */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
486 /* */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
487 /* */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
488 /* Be careful : in order to respect the rule about the */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
489 /* conversion "time => number of cylcles in this loop" */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
490 /* (Cf the functions: convert_nanosec_to_cycles() and */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
491 /* initialize_wait_loop() ) respect the following rules: */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
492 /* This function must be placed in Flash Memory and */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
493 /* compiled in 16 bits instructions length */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
494 /*-------------------------------------------------------*/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
495 void wait_ARM_cycles(SYS_UWORD32 cpt_loop)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
496 {
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
497 // C code:
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
498 // while (cpt_loop -- != 0);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
499
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
500 asm(" CMP A1, #0");
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
501 asm(" BEQ END_FUNCTION");
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
502
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
503 asm("LOOP_LINE: ");
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
504 asm(" SUB A1, A1, #1");
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
505 asm(" CMP A1, #0");
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
506 asm(" BNE LOOP_LINE");
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
507
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
508 asm("END_FUNCTION: ");
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
509 }
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
510
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
511 #endif /* (CHIPSET != 12)*/