FreeCalypso > hg > fc-magnetite

annotate src/cs/system/template/gsm_ds_int8_compact.template @ 600:8f50b202e81f

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board preprocessor conditionals: prep for more FC hw in the future This change eliminates the CONFIG_TARGET_FCDEV3B preprocessor symbol and all preprocessor conditionals throughout the code base that tested for it, replacing them with CONFIG_TARGET_FCFAM or CONFIG_TARGET_FCMODEM. These new symbols are specified as follows: CONFIG_TARGET_FCFAM is intended to cover all hardware designs created by Mother Mychaela under the FreeCalypso trademark. This family will include modem products (repackagings of the FCDEV3B, possibly with RFFE or even RF transceiver changes), and also my desired FreeCalypso handset product. CONFIG_TARGET_FCMODEM is intended to cover all FreeCalypso modem products (which will be firmware-compatible with the FCDEV3B if they use TI Rita transceiver, or will require a different fw build if we switch to one of Silabs Aero transceivers), but not the handset product. Right now this CONFIG_TARGET_FCMODEM preprocessor symbol is used to conditionalize everything dealing with MCSI. At the present moment the future of FC hardware evolution is still unknown: it is not known whether we will ever have any beyond-FCDEV3B hardware at all (contingent on uncertain funding), and if we do produce further FC hardware designs, it is not known whether they will retain the same FIC modem core (triband), if we are going to have a quadband design that still retains the classic Rita transceiver, or if we are going to switch to Silabs Aero II or some other transceiver. If we produce a quadband modem that still uses Rita, it will run exactly the same fw as the FCDEV3B thanks to the way we define TSPACT signals for the RF_FAM=12 && CONFIG_TARGET_FCFAM combination, and the current fcdev3b build target will be renamed to fcmodem. OTOH, if that putative quadband modem will be Aero-based, then it will require a different fw build target, the fcdev3b target will stay as it is, and the two targets will both define CONFIG_TARGET_FCFAM and CONFIG_TARGET_FCMODEM, but will have different RF_FAM numbers. But no matter which way we are going to evolve, it is not right to have conditionals on CONFIG_TARGET_FCDEV3B in places like ACI, and the present change clears the way for future evolution.
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 01 Apr 2019 01:05:24 +0000
parents 336edc558a30
children
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1 /*
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2 * Integrated Protocol Stack Linker command file (all components)
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3 *
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4 * Target : ARM
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5 *
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6 * Copyright (c) Texas Instruments 2002, Condat 2002
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7 *
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8 */
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9
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10 -c /* Autoinitialize variables at runtime */
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11
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12 /*********************************/
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13 /* SPECIFY THE SYSTEM MEMORY MAP */
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14 /*********************************/
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15
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16 MEMORY
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17 {
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18 /* CS0: Flash 8 Mbytes ****************************************************/
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19 /* Interrupt Vectors Table */
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20 I_MEM (RXI) : org = 0x00000000 len = 0x00000100
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21
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22 /* Boot Sector */
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23
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24 /* COMMENT1 stuff is commented out when using the 1.22e compiler */
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25 /* COMMENT2 stuff ditto, but when using 2.54 */
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26
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27 B_MEM (RXI) : org = 0x00000100 len = 0x00001f00
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28
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29 /* Magic Word for Calypso Boot ROM */
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30 MWC_MEM (RXI) : org = 0x00002000 len = 0x00000004 fill = 0x0000001
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31
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32 /* Program Memory */
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33
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34 P_MEM1 (RXI) : org = 0x00004000 len = 0x00000700
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35 P_MEM2 (RXI) : org = 0x00004700 len = 0x00000004
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36 P_MEM3 (RXI) : org = 0x00004704 len = 0x00400000
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37
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38 /* FFS Area */
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39 FFS_MEM (RX) : org = 0x00700000 len = 0x00100000
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40 /**************************************************************************/
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41
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42 /* CS1: External SRAM 1 Mbytes ********************************************/
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43 /* Data Memory */
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44 D_MEM1 (RW) : org = 0x01000000 len = 0x00100000
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45 /**************************************************************************/
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46
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47 /* CS2: External SRAM 8 Mbytes ********************************************/
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48 /* Data Memory */
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49 D_MEM2 (RW) : org = 0x01800000 len = 0x00800000
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50 /**************************************************************************/
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51
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52 /* CS6: Calypso Internal SRAM 512 kbytes **********************************/
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53 /* Code & Variables Memory */
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54 S_MEM (RXW) : org = 0x00800000 len = 0x00080000
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55 /**************************************************************************/
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56 }
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57
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58 /***********************************************/
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59 /* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */
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60 /***********************************************/
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61
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62 /*
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63 * Since the bootloader directly calls the INT_Initialize() routine located
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64 * in int.s, this int.s code must always be mapped at the same address
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65 * (usually in the second flash sector). Its length is about 0x500 bytes.
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66 * Then comes the code that need to be loaded into the internal RAM.
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67 */
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68
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69 SECTIONS
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70 {
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71 .intvecs : {} > I_MEM /* Interrupt Vectors Table */
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72 .monitor : > B_MEM /* Monitor Constants & Code */
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73 {
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74 $(CONST_BOOT_LIB)
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75 }
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76
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77 .inttext : {} > P_MEM1 /* int.s Code */
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78
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79 .bss_dar : > D_MEM1 /* DAR SWE Variables */
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80 {
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81 $(BSS_DAR_LIB)
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82 }
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83
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84 /*
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85 * The .bss section should not be split to ensure it is initialized to 0
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86 * each time the SW is reset. So the whole .bss is mapped either in D_MEM1
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87 * or in D_MEM2.
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88 */
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89
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90 .bss : > D_MEM1 | D_MEM2 /* Global & Static Variables */
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91 {
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92 $(BSS_BOOT_LIB)
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93 }
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94
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95 /*
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96 * All .bss sections, which must be mapped in internal RAM must be
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97 * grouped in order to initialized the corresponding memory to 0.
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98 * This initialization is done in int.s file before calling the Nucleus
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99 * routine.
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100 */
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101
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102 GROUP
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103 {
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104 S_D_Mem /* Label of start address of .bss section in Int. RAM */
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105 .DintMem
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106 {
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107
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108 /*
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109 * .bss sections of the application
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110 */
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111
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112 $(BSS_LIBS)
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113
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114 }
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115
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116 API_HISR_stack : {}
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117
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118 E_D_Mem /* Label of end address of .bss section in Int. RAM */
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119 } > S_MEM
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120
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121 /*
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122 * .text and .const sections which must be mapped in internal RAM.
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123 */
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124
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125 .ldfl : {} > P_MEM2 /* Used to know the start load address */
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126 GROUP load = P_MEM3, run = S_MEM
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127 {
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128 S_P_Mem /* Label of start address of .text & .const sections in Int. RAM */
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129 .PIntMem
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130 {
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131 /*
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132 * .text and .const sections of the application.
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133 *
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134 * The .veneer sections correspond exactly to .text:v&n sections
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135 * implementing the veneer functions. The .text:v$n -> .veneer
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136 * translation is performed by PTOOL software when PTOOL_OPTIONS
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137 * environement variable is set to veneer_section.
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138 */
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139
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140 $(CONST_LIBS)
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141
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142 }
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143 E_P_Mem /* Label of end address of .text and .const sections in Int. RAM */
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144 }
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145
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146 /*
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147 * The rest of the code is mapped in flash, however the trampolines
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148 * load address should be consistent with .text.
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149 */
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150
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151 COMMENT2START
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152 `trampolines load = P_MEM3, run = S_MEM
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153 COMMENT2END
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154
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155 .text : {} > P_MEM3 /* Code */
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156
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157 /*
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158 * The rest of the constants is mapped in flash.
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159 * The .cinit section should not be split.
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160 */
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161
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162 .cinit : {} > P_MEM3 /* Initialization Tables */
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163 .const : {} > P_MEM3 /* Constant Data */
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164 KadaAPI : {} > P_MEM3 /* ROMized CLDC */
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165
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166 .javastack: {} >> D_MEM1 | D_MEM2 /* Java stack */
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167
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168 .stackandheap : > D_MEM1 /* System Stacks, etc... */
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169 {
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170 /* Leave 20 32bit words for register pushes. */
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171 . = align(8);
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172 . += 20 * 4;
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173
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174 /* Stack for abort and/or undefined modes. */
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175 exception_stack = .;
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176
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177 /* Leave 38 32bit words for state saving on exceptions. */
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178 _xdump_buffer = .;
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179 . += 38 * 4;
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180 . = align(8);
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181
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182 /* Beginning of stacks and heap area - 2.75 kbytes (int.s) */
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183 stack_segment = .;
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184 . += 0xB00;
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185 }
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186
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187 .data : {} > D_MEM1 /* Initialized Data */
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188 .sysmem : {} > D_MEM1 /* Dynamic Memory Allocation Area */
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189
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190 }