FreeCalypso > hg > fc-magnetite
annotate src/cs/layer1/dyn_dwl_include/l1_dyn_dwl_msgty.h @ 700:800bf29abf31
audio mode load change from Tourmaline
Our FreeCalypso universe now has two kinds of audio mode config files:
the old 164 byte kind and the new 176 byte kind. We are not enabling
L1_NEW_AEC in Magnetite, only in Tourmaline, thus 164 byte audio mode
files are still native to Magnetite. But we still desire graceful
handling of the situation when a running Magnetite fw may load a
176 byte audio mode file (presumably with new AEC config), thus we
incorporate the same audio mode loading change which we implemented
in Tourmaline: if the loaded audio mode file is of the wrong kind,
the AEC config is cleared to default disabled state.
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Fri, 30 Jul 2021 03:55:52 +0000 |
| parents | 945cf7f506b2 |
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| rev | line source |
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945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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1 /************* Revision Controle System Header ************* |
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945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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2 * GSM Layer 1 software |
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src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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3 * L1_DYN_DWL_MSGTY.H |
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945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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4 * |
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945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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5 * Filename l1_dyn_dwl_msgty.h |
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945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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6 * Copyright 2004 (C) Texas Instruments |
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945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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7 * |
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945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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8 ************* Revision Controle System Header *************/ |
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945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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9 #if (L1_DYN_DSP_DWNLD == 1) |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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10 |
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945cf7f506b2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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11 typedef struct |
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src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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12 { |
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src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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13 UWORD16 patch_id; |
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Mychaela Falconia <falcon@freecalypso.org>
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14 }T_API_L1_CRC_NOT_OK; |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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15 typedef struct |
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945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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16 { |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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17 UWORD16 error; |
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src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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18 }T_API_L1_DYN_DWNLD_STOP; |
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src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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19 |
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src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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20 #endif // L1_DYN_DSP_DWNLD == 1 |
