fc-magnetite: src/cs/drivers/drv_core/timer/timer2.h annotate

annotate src/cs/drivers/drv_core/timer/timer2.h @ 598:717ed17d82c6

aci3 vocoder control revamped, AT@VSEL now works as it should The vocoder control code (hl_audio_drv.c) that came with the TCS3 version of ACI was totally broken in the Calypso config (VOCODER_FUNC_INTERFACE) and worked in the standard analog voice environment only by luck. This code has now been rewritten to work correctly with our Calypso platform and TCS211 L1, and our new AT@VSEL mechanism (automatic enabling and disabling of MCSI voice path as the modem enters and exits the voice call state) now also works as designed.

author	Mychaela Falconia <falcon@freecalypso.org>
date	Wed, 27 Mar 2019 23:44:35 +0000
parents	945cf7f506b2
children

rev	line source
0 945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1 /*******************************************************************************
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	2 TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	3
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	4 Property of Texas Instruments -- For Unrestricted Internal Use Only
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	5 Unauthorized reproduction and/or distribution is strictly prohibited. This
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	6 product is protected under copyright law and trade secret law as an
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	7 unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	8 rights reserved.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	9
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	10
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	11 Filename : timer2.h
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	12
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	13 Description :TIMER1
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	14
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	15 Project : drivers
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	16
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	17 Author : pmonteil@tif.ti.com Patrice Monteil.
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	18
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	19 Version number : 1.4
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	20
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	21 Date and time : 02/15/01 15:47:05
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	22
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	23 Previous delta : 02/15/01 15:47:05
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	24
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	25 SCCS file : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/mod/emu_p/EMU_P_FRED/drivers1/common/SCCS/s.timer2.h
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	26
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	27 Sccs Id (SID) : '@(#) timer2.h 1.4 02/15/01 15:47:05 '
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	28
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	29
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	30
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	31 *****************************************************************************/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	32
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	33 #include "l1sw.cfg"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	34
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	35 #if (OP_L1_STANDALONE == 0)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	36 #include "main/sys_types.h"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	37 #else
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	38 #include "sys_types.h"
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	39 #endif
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	40
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	41
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	42 /** DIONE TIMERs configuration register **/
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	43
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	44 #define D_TIMER_ADDR 0xfffe6800
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	45
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	46 #define D_TIMER_CNTL_MASK 0x001f
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	47
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	48 #define CNTL_D_TIMER_OFFSET 0x0000
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	49 #define LOAD_D_TIMER_OFFSET 0x0002
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	50 #define READ_D_TIMER_OFFSET 0x0004
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	51
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	52 #define D_TIMER_CNTL (D_TIMER_ADDR+CNTL_D_TIMER_OFFSET)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	53 #define D_TIMER_LOAD (D_TIMER_ADDR+LOAD_D_TIMER_OFFSET)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	54 #define D_TIMER_READ (D_TIMER_ADDR+READ_D_TIMER_OFFSET)
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	55
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	56 #define D_TIMER_ST 0x0001 /* bit 0 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	57 #define D_TIMER_AR 0x0002 /* bit 1 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	58 #define D_TIMER_PTV 0x001c /* bits 4:2 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	59 #define D_TIMER_CLK_EN 0x0020 /* bit 5 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	60 #define D_TIMER_RUN 0x0021 /* bit 5 ,0 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	61
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	62 #define LOAD_TIM 0xffff /* bits 15:0 */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	63
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	64
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	65
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	66
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	67
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	68 /* ----- Prototypes ----- */
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	69 SYS_UWORD16 Dtimer2_Get_cntlreg(void);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	70
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	71 void Dtimer2_AR(SYS_UWORD16 Ar);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	72
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	73 void Dtimer2_PTV(SYS_UWORD16 Ptv);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	74
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	75 void Dtimer2_Clken(SYS_UWORD16 En);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	76
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	77 void Dtimer2_Start (SYS_UWORD16 startStop);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	78
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	79 void Dtimer2_Init_cntl (SYS_UWORD16 St, SYS_UWORD16 Reload, SYS_UWORD16 clockScale, SYS_UWORD16 clkon);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	80
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	81 void Dtimer2_WriteValue (SYS_UWORD16 value);
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	82
945cf7f506b2 src/cs: chipsetsw import from tcs211-fcmodem Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	83 SYS_UWORD16 Dtimer2_ReadValue (void);

FreeCalypso > hg > fc-magnetite

annotate src/cs/drivers/drv_core/timer/timer2.h @ 598:717ed17d82c6