FreeCalypso > hg > fc-magnetite
annotate src/cs/system/template/gsm_ds_motc155.template @ 685:3fb7384e820d
tpudrv12.h: FCDEV3B goes back to being itself
A while back we had the idea of a FreeCalypso modem family whereby our
current fcdev3b target would some day morph into fcmodem, with multiple
FC modem family products, potentially either triband or quadband, being
firmware-compatible with each other and with our original FCDEV3B. But
in light of the discovery of Tango modules that earlier idea is now being
withdrawn: instead the already existing Tango hw is being adopted into
our FreeCalypso family.
Tango cannot be firmware-compatible with triband OM/FCDEV3B targets
because the original quadband RFFE on Tango modules is wired in TI's
original Leonardo arrangement. Because this Leonardo/Tango way is now
becoming the official FreeCalypso way of driving quadband RFFEs thanks
to the adoption of Tango into our FC family, our earlier idea of
extending FIC's triband RFFE control signals with TSPACT5 no longer makes
much sense - we will probably never produce any new hardware with that
once-proposed arrangement. Therefore, that triband-or-quadband FCFAM
provision is being removed from the code base, and FCDEV3B goes back to
being treated the same way as CONFIG_TARGET_GTAMODEM for RFFE control
purposes.
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Thu, 24 Sep 2020 21:03:08 +0000 |
| parents | ae18f9aad7ce |
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| rev | line source |
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1 /* |
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2 * Integrated Protocol Stack Linker command file (all components) |
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3 * |
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4 * Target : ARM |
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5 * |
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6 * Copyright (c) Texas Instruments 2002, Condat 2002 |
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7 * |
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8 * This version of the linker script template has been concocted |
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9 * by Spacefalcon the Outlaw based on previous hacks. |
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10 */ |
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11 |
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12 -c /* Autoinitialize variables at runtime */ |
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13 |
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14 /*********************************/ |
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15 /* SPECIFY THE SYSTEM MEMORY MAP */ |
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16 /*********************************/ |
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17 |
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18 MEMORY |
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19 { |
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20 /* CS0: Flash 4 Mbytes ****************************************************/ |
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21 /* Interrupt Vectors Table */ |
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22 I_MEM (RXI) : org = 0x00000000 len = 0x00000100 |
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23 |
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24 /* Boot Sector */ |
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25 B_MEM (RXI) : org = 0x00000100 len = 0x00001f00 |
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26 |
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27 /* Magic Word for Calypso Boot ROM */ |
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28 MWC_MEM (RXI) : org = 0x00002000 len = 0x00000004 fill = 0x0000001 |
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29 |
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30 /* Program Memory */ |
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31 P_MEM1 (RXI) : org = 0x000200E0 len = 0x00000700 |
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32 P_MEM2 (RXI) : org = 0x000207E0 len = 0x00000004 |
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33 P_MEM3 (RXI) : org = 0x000207E4 len = 0x00400000 |
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34 |
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35 /* FFS Area */ |
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36 FFS_MEM (RX) : org = 0x00700000 len = 0x000D0000 |
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37 /**************************************************************************/ |
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38 |
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39 /* CS1: External SRAM 2 Mbytes ********************************************/ |
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40 /* Data Memory */ |
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41 |
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42 /* We do the same splitting hack as on other targets */ |
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43 |
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44 D_MEM1 (RW) : org = 0x01000000 len = 0x00100000 |
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45 D_MEM2 (RW) : org = 0x01100000 len = 0x00100000 |
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46 /**************************************************************************/ |
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47 |
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48 /* CS6: Calypso Internal SRAM 256 kbytes **********************************/ |
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49 /* Code & Variables Memory */ |
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50 S_MEM (RXW) : org = 0x00800000 len = 0x00040000 |
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51 /**************************************************************************/ |
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52 } |
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53 |
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54 /***********************************************/ |
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55 /* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */ |
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56 /***********************************************/ |
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57 |
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58 /* |
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59 * Since the bootloader directly calls the INT_Initialize() routine located |
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60 * in int.s, this int.s code must always be mapped at the same address |
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61 * (usually in the second flash sector). Its length is about 0x500 bytes. |
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62 * Then comes the code that need to be loaded into the internal RAM. |
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63 */ |
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64 |
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65 SECTIONS |
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66 { |
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67 .intvecs : {} > I_MEM /* Interrupt Vectors Table */ |
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68 .monitor : > B_MEM /* Monitor Constants & Code */ |
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69 { |
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70 $(CONST_BOOT_LIB) |
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71 } |
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72 |
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73 .inttext : {} > P_MEM1 /* int.s Code */ |
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74 |
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75 .bss_dar : > D_MEM1 /* DAR SWE Variables */ |
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76 { |
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77 $(BSS_DAR_LIB) |
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78 } |
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79 |
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80 /* |
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81 * The .bss section should not be split to ensure it is initialized to 0 |
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82 * each time the SW is reset. So the whole .bss is mapped either in D_MEM1 |
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83 * or in D_MEM2. |
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84 * |
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85 * Falcon's note for K5A3281: see the comments above where the memory |
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86 * regions are defined. |
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87 */ |
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88 |
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89 .bss : > D_MEM1 | D_MEM2 /* Global & Static Variables */ |
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90 { |
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91 $(BSS_BOOT_LIB) |
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92 } |
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93 |
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94 /* |
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95 * All .bss sections, which must be mapped in internal RAM must be |
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96 * grouped in order to initialized the corresponding memory to 0. |
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97 * This initialization is done in int.s file before calling the Nucleus |
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98 * routine. |
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99 */ |
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100 |
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101 GROUP |
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102 { |
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103 S_D_Mem /* Label of start address of .bss section in Int. RAM */ |
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104 .DintMem |
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105 { |
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106 |
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107 /* |
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108 * .bss sections of the application |
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109 */ |
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110 |
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111 $(BSS_LIBS) |
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112 |
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113 } |
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114 |
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115 API_HISR_stack : {} |
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116 |
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117 E_D_Mem /* Label of end address of .bss section in Int. RAM */ |
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118 } > S_MEM |
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119 |
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120 /* |
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121 * .text and .const sections which must be mapped in internal RAM. |
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122 */ |
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123 |
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124 .ldfl : {} > P_MEM2 /* Used to know the start load address */ |
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125 GROUP load = P_MEM3, run = S_MEM |
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126 { |
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127 S_P_Mem /* Label of start address of .text & .const sections in Int. RAM */ |
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128 .PIntMem |
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129 { |
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130 /* |
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131 * .text and .const sections of the application. |
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132 * |
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133 * The .veneer sections correspond exactly to .text:v&n sections |
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134 * implementing the veneer functions. The .text:v$n -> .veneer |
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135 * translation is performed by PTOOL software when PTOOL_OPTIONS |
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136 * environement variable is set to veneer_section. |
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137 */ |
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138 |
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139 $(CONST_LIBS) |
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140 |
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141 } |
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142 E_P_Mem /* Label of end address of .text and .const sections in Int. RAM */ |
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143 } |
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144 |
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145 /* |
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146 * The rest of the code is mapped in flash, however the trampolines |
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147 * load address should be consistent with .text. |
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148 */ |
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149 COMMENT2START |
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150 `trampolines load = P_MEM3, run = S_MEM |
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151 COMMENT2END |
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152 |
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153 .text : {} > P_MEM3 /* Code */ |
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154 |
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155 /* |
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156 * The rest of the constants is mapped in flash. |
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157 * The .cinit section should not be split. |
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158 */ |
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159 |
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160 .cinit : {} > P_MEM3 /* Initialization Tables */ |
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161 .const : {} > P_MEM3 /* Constant Data */ |
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162 KadaAPI : {} > P_MEM3 /* ROMized CLDC */ |
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163 |
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164 .javastack: {} >> D_MEM1 | D_MEM2 /* Java stack */ |
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165 |
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166 .stackandheap : > D_MEM1 /* System Stacks, etc... */ |
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167 { |
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168 /* Leave 20 32bit words for register pushes. */ |
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169 . = align(8); |
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170 . += 20 * 4; |
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171 |
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172 /* Stack for abort and/or undefined modes. */ |
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173 exception_stack = .; |
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174 |
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175 /* Leave 38 32bit words for state saving on exceptions. */ |
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176 _xdump_buffer = .; |
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177 . += 38 * 4; |
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178 . = align(8); |
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179 |
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180 /* Beginning of stacks and heap area - 2.75 kbytes (int.s) */ |
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181 stack_segment = .; |
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182 . += 0xB00; |
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183 } |
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184 |
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185 .data : {} > D_MEM1 /* Initialized Data */ |
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186 .sysmem : {} > D_MEM1 /* Dynamic Memory Allocation Area */ |
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187 |
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188 } |
