annotate src/cs/layer1/dsp1/leadboot.c @ 629:3231dd9b38c1

armio.c: make GPIOs 8 & 13 outputs driving 1 on all "classic" targets Calypso GPIOs 8 & 13 are pinmuxed with MCUEN1 & MCUEN2, respectively, and on powerup these pins are MCUEN, i.e., outputs driving 1. TI's code for C-Sample and earlier turns them into GPIOs configured as outputs also driving 1 - so far, so good - but TI's code for BOARD 41 (which covers D-Sample, Leonardo and all real world Calypso devices derived from the latter) switches them from MCUEN to GPIOs, but then leaves them as inputs. Given that the hardware powerup state of these two pins is outputs driving 1, every Calypso board design MUST be compatible with such driving; typically these GPIO signals will be either unused and unconnected or connected as outputs driving some peripheral. Turning these pins into GPIO inputs will result in floating inputs on every reasonably-wired board, thus I am convinced that this configuration is nothing but a bug on the part of whoever wrote this code at TI. This floating input bug had already been fixed earlier for GTA modem and FCDEV3B targets; the present change makes the fix unconditional for all "classic" targets. The newly affected targets are D-Sample, Leonardo, Tango and GTM900.
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 02 Jan 2020 05:38:26 +0000
parents 50a15a54801e
children
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1 /*
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2 * This module is from the LoCosto source, and the char array found herein
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3 * has been confirmed to match the one in the Leonardo binary lib as well.
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4 */
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6 const unsigned char bootCode[] = {
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8 /* Tag */ 0x00, 0x00, 0x00, 0x00,
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9 /* Vers */ 0x03, 0x00, 0x00, 0x00,
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11 /* size */ 0x31, 0x00, 0x00, 0x00,
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12 /* addr */ 0x00, 0xf8, 0x00, 0x00,
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13
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14 0xF8,0x69,0x29,0x00,0x02,0x00,0x1F,0xEA,0x14,0x77,0x00,0x00,0x7F,0x76,0x01,0x00,
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15 0x7F,0x60,0x04,0x00,0x20,0xF8,0x10,0x01,0x14,0x72,0x00,0x08,0x7F,0x76,0x01,0x00,
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16 0x7F,0x60,0x02,0x00,0x20,0xF8,0x08,0x01,0x7E,0x12,0x7C,0x3C,0x7D,0x13,0x11,0x89,
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17 0x4C,0xF8,0x1D,0x01,0x30,0xF0,0xFF,0xFF,0xE2,0xF4,0x89,0x6D,0x12,0x77,0x00,0x08,
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18 0xF8,0x11,0x14,0x00,0x4E,0xF8,0x29,0x01,0xF8,0x47,0x11,0x00,0x92,0x7F,0x73,0xF0,
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
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19 0x2D,0x01,0x13,0x88,0xF8,0x47,0x11,0x00,0x89,0xE5,0x7F,0x76,0x01,0x00,0x73,0xF0,
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
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20 0x08,0x01,
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21
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22 /* size */ 0x29, 0x00, 0x00, 0x00,
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23 /* addr */ 0x00, 0xfe, 0x00, 0x00,
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24
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
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25 0x18,0x77,0x80,0x07,0xF8,0x69,0x1D,0x00,0x28,0x00,0x28,0x77,0x92,0x24,0xF8,0x76,
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26 0x11,0x00,0x01,0x00,0xF8,0x75,0x11,0x00,0x00,0xF9,0x06,0x77,0x00,0x18,0x07,0x77,
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27 0x00,0x2D,0x26,0x77,0x10,0x00,0x00,0x77,0x00,0x00,0x01,0x77,0xFF,0xFF,0x00,0xEA,
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28 0x95,0xF4,0x11,0x77,0x00,0x01,0x12,0x77,0x00,0xF8,0x20,0xF0,0x31,0xF8,0x12,0x08,
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29 0x10,0xF0,0x01,0x00,0x13,0x80,0x95,0xF4,0x13,0x47,0x91,0x7C,0x00,0xF8,0x73,0xF0,
50a15a54801e src/cs/layer1: import from tcs211-l1-reconst project
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30 0x00,0x01,
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31
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32 /* size */ 0x04, 0x00, 0x00, 0x00,
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33 /* addr */ 0x80, 0xff, 0x00, 0x00,
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34
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35 0x73,0xF0,0x00,0xFE,0x95,0xF4,0x95,0xF4,
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36 /* Final record */
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37 /* size */ 0x00, 0x00, 0x00, 0x00,
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38 /* addr */ 0x00, 0xf8, 0x00, 0x00,
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39
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40 };