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annotate src/cs/layer1/dyn_dwl_include/l1_dyn_dwl_const.h @ 605:07d0dc4431f4

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bootloader.s: same MEMIF fix as in int.s plus DPLL BYPASS fix Both MEMIF and DPLL settings are now the same between int.s and bootloader.s assembly code paths. Previously bootloader.s was setting DPLL BYPASS /2 mode, which persisted until _INT_Initialize code with the bootloader body omitted, or was changed to /1 in the hardware init function in the bootloader.lib:start.obj module.
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 17 Jun 2019 18:40:32 +0000
parents 50a15a54801e
children
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1 /************* Revision Controle System Header *************
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2 * GSM Layer 1 software
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3 * L1_DYN_DWL_CONST.H
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4 *
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5 * Filename l1_dyn_dwl_const.h.h
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6 * Copyright 2004 (C) Texas Instruments
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7 *
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8 ************* Revision Controle System Header *************/
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9 #if (L1_DYN_DSP_DWNLD == 1)
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11 #ifndef _L1_DYN_DWL_CONST_H_
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12 #define _L1_DYN_DWL_CONST_H_
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14 /* DSP dynamic download background task id */
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15 #define C_BGD_DSP_DYN_DWNLD 9
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17 #define RED 1
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18 #define GREEN 0
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19 #define MAX_NUM_OF_PATCH_IDS 5
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20 #define MAX_NUM_OF_SEMAPHORES 6
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22 #define NUM_OF_DYN_DWNLD_PRIMITIVES 6
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24 #define NUM_WORDS_COPY_API 256 // even value mandatory
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25 #define START_API_DWNLD_AREA 0x1808 // 0x1808
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26 #define SIZE_API_DWNLD_AREA 0x7F8 // 0x800
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27 #define START_API_DWNLD_AREA_DURING_E2 0x10C1 // 0x10BE
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28 #define SIZE_API_DWNLD_AREA_DURING_E2 0x15B // 0x410
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29 #define MCU_API_BASE_ADDRESS 0xFFD00000L
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30 #define DSP_API_BASE_ADDRESS 0x800
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33 /* Dynamic Download API base address */
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34 #define C_DYN_DWNLD_API_BASE_ADDRESS 0x17F6
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35 #define HEADER_PATCH_SIZE 4
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37 #if(CODE_VERSION == SIMULATION)
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38 #define CRC_SIMU_OK 0xCAFE
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39 #define SIZE_DWNLD_AREA_SIMU 2048
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40 #endif
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42 #define TRUE 1
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43 #define FALSE 0
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46 /* Define commands MCU/DSP*/
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47 #define C_DWL_DOWNLOAD_CTRL_DSP_ACK 0
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48 #define C_DWL_DOWNLOAD_CTRL_DOWNLOAD 1
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49 #define C_DWL_DOWNLOAD_CTRL_INSTALL 2
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50 #define C_DWL_DOWNLOAD_CTRL_UNINSTALL 3
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51 #define C_DWL_DOWNLOAD_CTRL_ABORT 4
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52 #define C_DWL_DOWNLOAD_CTRL_INIT 5
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53 #define C_DWL_ERR_RESET 0
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54
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55 #endif // _L1_DYN_DWL_CONST_H_
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56 #endif // L1_DYN_DSP_DWNLD