FreeCalypso > hg > fc-magnetite
annotate src/cs/layer1/dyn_dwl_include/l1_dyn_dwl_signa.h @ 639:026c98f757a6
tpudrv12.h & targets/gtm900.h: our current support is for MGC2GSMT version only
As it turns out, there exist two different Huawei-made hw platforms both
bearing the marketing name GTM900-B: one is MG01GSMT, the other is MGC2GSMT.
The two are NOT fw-compatible: aside from flash chip differences which
should be handled by autodetection, the two hw platforms are already known
to have different RFFEs with different control signals, and there may be
other differences not yet known. Our current gtm900 build target is for
MGC2GSMT only; we do not yet have a specimen of MG01GSMT on hand, hence
no support for that version will be possible until and unless someone
provides one.
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Thu, 30 Jan 2020 18:19:01 +0000 |
| parents | 945cf7f506b2 |
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| rev | line source |
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945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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1 /************* Revision Controle System Header ************* |
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945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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2 * GSM Layer 1 software |
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src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
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3 * L1_DYN_DWL_SIGNA.H |
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src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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4 * |
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945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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5 * Filename l1_dyn_dwl_signa.h |
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src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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6 * Copyright 2004 (C) Texas Instruments |
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945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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7 * |
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945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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8 ************* Revision Controle System Header *************/ |
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945cf7f506b2
src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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9 #if (L1_DYN_DSP_DWNLD == 1) |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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10 |
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parents:
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11 #ifndef _L1_DYN_DWL_SIGNA_H_ |
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src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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12 #define _L1_DYN_DWL_SIGNA_H_ |
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src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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13 |
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src/cs: chipsetsw import from tcs211-fcmodem
Mychaela Falconia <falcon@freecalypso.org>
parents:
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14 #define P_DYN_DWNLD 0x41 |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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parents:
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16 // Messages L1S -> L1A |
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17 #define L1_DYN_DWNLD_STOP_CON ( ( P_DYN_DWNLD << 8 ) | 0x02 ) |
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18 |
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parents:
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19 // Messages API HISR -> L1A // |
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parents:
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20 #define API_L1_DYN_DWNLD_START_CON ( ( P_DYN_DWNLD << 8 ) | 0x03 ) |
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21 #define API_L1_DYN_DWNLD_FINISHED ( ( P_DYN_DWNLD << 8 ) | 0x04 ) |
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Mychaela Falconia <falcon@freecalypso.org>
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22 #define API_L1_DYN_DWNLD_STOP ( ( P_DYN_DWNLD << 8 ) | 0x05 ) |
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23 #define API_L1_CRC_NOT_OK ( ( P_DYN_DWNLD << 8 ) | 0x07 ) |
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24 #define API_L1_CRC_OK ( ( P_DYN_DWNLD << 8 ) | 0x08 ) |
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25 #define API_L1_DYN_DWNLD_UNINST_OK ( ( P_DYN_DWNLD << 8 ) | 0x09 ) |
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parents:
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27 #endif //_L1_DYN_DWL_SIGNA_H_ |
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parents:
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parents:
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29 #endif // L1_DYN_DSP_DWNLD |
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